1/* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7#ifndef _DDR3_HWS_HW_TRAINING_DEF_H 8#define _DDR3_HWS_HW_TRAINING_DEF_H 9 10#define SAR_DDR3_FREQ_MASK 0xfe00000 11#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | \ 12 ((fab & 0xf) << 24)) 13 14#define MAX_CS 4 15 16#define MIN_DIMM_ADDR 0x50 17#define FAR_END_DIMM_ADDR 0x50 18#define MAX_DIMM_ADDR 0x60 19 20#define SDRAM_CS_SIZE 0xfffffff 21#define SDRAM_CS_BASE 0x0 22#define SDRAM_DIMM_SIZE 0x80000000 23 24#define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) 25#define CPU_MRVL_ID_OFFSET 0x10 26#define SAR1_CPU_CORE_MASK 0x38000000 27#define SAR1_CPU_CORE_OFFSET 27 28 29#define NEW_FABRIC_TWSI_ADDR 0x4e 30#ifdef DB_784MP_GP 31#define BUS_WIDTH_ECC_TWSI_ADDR 0x4e 32#else 33#define BUS_WIDTH_ECC_TWSI_ADDR 0x4f 34#endif 35#define MV_MAX_DDR3_STATIC_SIZE 50 36#define MV_DDR3_MODES_NUMBER 30 37 38#define RESUME_RL_PATTERNS_ADDR 0xfe0000 39#define RESUME_RL_PATTERNS_SIZE 0x100 40#define RESUME_TRAINING_VALUES_ADDR (RESUME_RL_PATTERNS_ADDR + \ 41 RESUME_RL_PATTERNS_SIZE) 42#define RESUME_TRAINING_VALUES_MAX 0xcd0 43#define BOOT_INFO_ADDR (RESUME_RL_PATTERNS_ADDR + 0x1000) 44#define CHECKSUM_RESULT_ADDR (BOOT_INFO_ADDR + 0x1000) 45#define NUM_OF_REGISTER_ADDR (CHECKSUM_RESULT_ADDR + 4) 46#define SUSPEND_MAGIC_WORD 0xdeadb002 47#define REGISTER_LIST_END 0xffffffff 48 49/* MISC */ 50#define INTER_REGS_BASE SOC_REGS_PHY_BASE 51 52/* DDR */ 53#define REG_SDRAM_CONFIG_ADDR 0x1400 54#define REG_SDRAM_CONFIG_MASK 0x9fffffff 55#define REG_SDRAM_CONFIG_RFRS_MASK 0x3fff 56#define REG_SDRAM_CONFIG_WIDTH_OFFS 15 57#define REG_SDRAM_CONFIG_REGDIMM_OFFS 17 58#define REG_SDRAM_CONFIG_ECC_OFFS 18 59#define REG_SDRAM_CONFIG_IERR_OFFS 19 60#define REG_SDRAM_CONFIG_PUPRSTDIV_OFFS 28 61#define REG_SDRAM_CONFIG_RSTRD_OFFS 30 62 63#define REG_SDRAM_PINS_MUX 0x19d4 64 65#define REG_DUNIT_CTRL_LOW_ADDR 0x1404 66#define REG_DUNIT_CTRL_LOW_2T_OFFS 3 67#define REG_DUNIT_CTRL_LOW_2T_MASK 0x3 68#define REG_DUNIT_CTRL_LOW_DPDE_OFFS 14 69 70#define REG_SDRAM_TIMING_LOW_ADDR 0x1408 71#define REG_SDRAM_TIMING_HIGH_ADDR 0x140c 72#define REG_SDRAM_TIMING_H_R2R_OFFS 7 73#define REG_SDRAM_TIMING_H_R2R_MASK 0x3 74#define REG_SDRAM_TIMING_H_R2W_W2R_OFFS 9 75#define REG_SDRAM_TIMING_H_R2W_W2R_MASK 0x3 76#define REG_SDRAM_TIMING_H_W2W_OFFS 11 77#define REG_SDRAM_TIMING_H_W2W_MASK 0x1f 78#define REG_SDRAM_TIMING_H_R2R_H_OFFS 19 79#define REG_SDRAM_TIMING_H_R2R_H_MASK 0x7 80#define REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS 22 81#define REG_SDRAM_TIMING_H_R2W_W2R_H_MASK 0x7 82 83#define REG_SDRAM_ADDRESS_CTRL_ADDR 0x1410 84#define REG_SDRAM_ADDRESS_SIZE_OFFS 2 85#define REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS 18 86#define REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS 4 87 88#define REG_SDRAM_OPEN_PAGES_ADDR 0x1414 89#define REG_SDRAM_OPERATION_CS_OFFS 8 90 91#define REG_SDRAM_OPERATION_ADDR 0x1418 92#define REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS 24 93#define REG_SDRAM_OPERATION_CWA_DATA_OFFS 20 94#define REG_SDRAM_OPERATION_CWA_DATA_MASK 0xf 95#define REG_SDRAM_OPERATION_CWA_RC_OFFS 16 96#define REG_SDRAM_OPERATION_CWA_RC_MASK 0xf 97#define REG_SDRAM_OPERATION_CMD_MR0 0xf03 98#define REG_SDRAM_OPERATION_CMD_MR1 0xf04 99#define REG_SDRAM_OPERATION_CMD_MR2 0xf08 100#define REG_SDRAM_OPERATION_CMD_MR3 0xf09 101#define REG_SDRAM_OPERATION_CMD_RFRS 0xf02 102#define REG_SDRAM_OPERATION_CMD_CWA 0xf0e 103#define REG_SDRAM_OPERATION_CMD_RFRS_DONE 0xf 104#define REG_SDRAM_OPERATION_CMD_MASK 0xf 105#define REG_SDRAM_OPERATION_CS_OFFS 8 106 107#define REG_OUDDR3_TIMING_ADDR 0x142c 108 109#define REG_SDRAM_MODE_ADDR 0x141c 110 111#define REG_SDRAM_EXT_MODE_ADDR 0x1420 112 113#define REG_DDR_CONT_HIGH_ADDR 0x1424 114 115#define REG_ODT_TIME_LOW_ADDR 0x1428 116#define REG_ODT_ON_CTL_RD_OFFS 12 117#define REG_ODT_OFF_CTL_RD_OFFS 16 118#define REG_SDRAM_ERROR_ADDR 0x1454 119#define REG_SDRAM_AUTO_PWR_SAVE_ADDR 0x1474 120#define REG_ODT_TIME_HIGH_ADDR 0x147c 121 122#define REG_SDRAM_INIT_CTRL_ADDR 0x1480 123#define REG_SDRAM_INIT_CTRL_OFFS 0 124#define REG_SDRAM_INIT_CKE_ASSERT_OFFS 2 125#define REG_SDRAM_INIT_RESET_DEASSERT_OFFS 3 126#define REG_SDRAM_INIT_RESET_MASK_OFFS 1 127 128#define REG_SDRAM_ODT_CTRL_LOW_ADDR 0x1494 129 130#define REG_SDRAM_ODT_CTRL_HIGH_ADDR 0x1498 131#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0x0 132#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA 0x3 133 134#define REG_DUNIT_ODT_CTRL_ADDR 0x149c 135#define REG_DUNIT_ODT_CTRL_OVRD_OFFS 8 136#define REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS 9 137 138#define REG_DRAM_FIFO_CTRL_ADDR 0x14a0 139 140#define REG_DRAM_AXI_CTRL_ADDR 0x14a8 141#define REG_DRAM_AXI_CTRL_AXIDATABUSWIDTH_OFFS 0 142 143#define REG_METAL_MASK_ADDR 0x14b0 144#define REG_METAL_MASK_MASK 0xdfffffff 145#define REG_METAL_MASK_RETRY_OFFS 0 146 147#define REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR 0x14c0 148 149#define REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR 0x14c4 150#define REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR 0x14c8 151#define REG_DRAM_MAIN_PADS_CAL_ADDR 0x14cc 152 153#define REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR 0x17c8 154 155#define REG_CS_SIZE_SCRATCH_ADDR 0x1504 156#define REG_DYNAMIC_POWER_SAVE_ADDR 0x1520 157#define REG_DDR_IO_ADDR 0x1524 158#define REG_DDR_IO_CLK_RATIO_OFFS 15 159 160#define REG_DFS_ADDR 0x1528 161#define REG_DFS_DLLNEXTSTATE_OFFS 0 162#define REG_DFS_BLOCK_OFFS 1 163#define REG_DFS_SR_OFFS 2 164#define REG_DFS_ATSR_OFFS 3 165#define REG_DFS_RECONF_OFFS 4 166#define REG_DFS_CL_NEXT_STATE_OFFS 8 167#define REG_DFS_CL_NEXT_STATE_MASK 0xf 168#define REG_DFS_CWL_NEXT_STATE_OFFS 12 169#define REG_DFS_CWL_NEXT_STATE_MASK 0x7 170 171#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538 172#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1f 173#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8 174 175#define REG_READ_DATA_READY_DELAYS_ADDR 0x153c 176#define REG_READ_DATA_READY_DELAYS_MASK 0x1f 177#define REG_READ_DATA_READY_DELAYS_OFFS 8 178 179#define START_BURST_IN_ADDR 1 180 181#define REG_DRAM_TRAINING_SHADOW_ADDR 0x18488 182#define REG_DRAM_TRAINING_ADDR 0x15b0 183#define REG_DRAM_TRAINING_LOW_FREQ_OFFS 0 184#define REG_DRAM_TRAINING_PATTERNS_OFFS 4 185#define REG_DRAM_TRAINING_MED_FREQ_OFFS 2 186#define REG_DRAM_TRAINING_WL_OFFS 3 187#define REG_DRAM_TRAINING_RL_OFFS 6 188#define REG_DRAM_TRAINING_DQS_RX_OFFS 15 189#define REG_DRAM_TRAINING_DQS_TX_OFFS 16 190#define REG_DRAM_TRAINING_CS_OFFS 20 191#define REG_DRAM_TRAINING_RETEST_OFFS 24 192#define REG_DRAM_TRAINING_DFS_FREQ_OFFS 27 193#define REG_DRAM_TRAINING_DFS_REQ_OFFS 29 194#define REG_DRAM_TRAINING_ERROR_OFFS 30 195#define REG_DRAM_TRAINING_AUTO_OFFS 31 196#define REG_DRAM_TRAINING_RETEST_PAR 0x3 197#define REG_DRAM_TRAINING_RETEST_MASK 0xf8ffffff 198#define REG_DRAM_TRAINING_CS_MASK 0xff0fffff 199#define REG_DRAM_TRAINING_PATTERNS_MASK 0xff0f0000 200 201#define REG_DRAM_TRAINING_1_ADDR 0x15b4 202#define REG_DRAM_TRAINING_1_TRNBPOINT_OFFS 16 203 204#define REG_DRAM_TRAINING_2_ADDR 0x15b8 205#define REG_DRAM_TRAINING_2_OVERRUN_OFFS 17 206#define REG_DRAM_TRAINING_2_FIFO_RST_OFFS 4 207#define REG_DRAM_TRAINING_2_RL_MODE_OFFS 3 208#define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2 209#define REG_DRAM_TRAINING_2_ECC_MUX_OFFS 1 210#define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0 211 212#define REG_DRAM_TRAINING_PATTERN_BASE_ADDR 0x15bc 213#define REG_DRAM_TRAINING_PATTERN_BASE_OFFS 3 214 215#define REG_TRAINING_DEBUG_2_ADDR 0x15c4 216#define REG_TRAINING_DEBUG_2_OFFS 16 217#define REG_TRAINING_DEBUG_2_MASK 0x3 218 219#define REG_TRAINING_DEBUG_3_ADDR 0x15c8 220#define REG_TRAINING_DEBUG_3_OFFS 3 221#define REG_TRAINING_DEBUG_3_MASK 0x7 222 223#define MR_CS_ADDR_OFFS 4 224 225#define REG_DDR3_MR0_ADDR 0x15d0 226#define REG_DDR3_MR0_CS_ADDR 0x1870 227#define REG_DDR3_MR0_CL_MASK 0x74 228#define REG_DDR3_MR0_CL_OFFS 2 229#define REG_DDR3_MR0_CL_HIGH_OFFS 3 230#define CL_MASK 0xf 231 232#define REG_DDR3_MR1_ADDR 0x15d4 233#define REG_DDR3_MR1_CS_ADDR 0x1874 234#define REG_DDR3_MR1_RTT_MASK 0xfffffdbb 235#define REG_DDR3_MR1_DLL_ENA_OFFS 0 236#define REG_DDR3_MR1_RTT_DISABLED 0x0 237#define REG_DDR3_MR1_RTT_RZQ2 0x40 238#define REG_DDR3_MR1_RTT_RZQ4 0x2 239#define REG_DDR3_MR1_RTT_RZQ6 0x42 240#define REG_DDR3_MR1_RTT_RZQ8 0x202 241#define REG_DDR3_MR1_RTT_RZQ12 0x4 242/* WL-disabled, OB-enabled */ 243#define REG_DDR3_MR1_OUTBUF_WL_MASK 0xffffef7f 244/* Output Buffer Disabled */ 245#define REG_DDR3_MR1_OUTBUF_DIS_OFFS 12 246#define REG_DDR3_MR1_WL_ENA_OFFS 7 247#define REG_DDR3_MR1_WL_ENA 0x80 /* WL Enabled */ 248#define REG_DDR3_MR1_ODT_MASK 0xfffffdbb 249 250#define REG_DDR3_MR2_ADDR 0x15d8 251#define REG_DDR3_MR2_CS_ADDR 0x1878 252#define REG_DDR3_MR2_CWL_OFFS 3 253#define REG_DDR3_MR2_CWL_MASK 0x7 254#define REG_DDR3_MR2_ODT_MASK 0xfffff9ff 255#define REG_DDR3_MR3_ADDR 0x15dc 256#define REG_DDR3_MR3_CS_ADDR 0x187c 257 258#define REG_DDR3_RANK_CTRL_ADDR 0x15e0 259#define REG_DDR3_RANK_CTRL_CS_ENA_MASK 0xf 260#define REG_DDR3_RANK_CTRL_MIRROR_OFFS 4 261 262#define REG_ZQC_CONF_ADDR 0x15e4 263 264#define REG_DRAM_PHY_CONFIG_ADDR 0x15ec 265#define REG_DRAM_PHY_CONFIG_MASK 0x3fffffff 266 267#define REG_ODPG_CNTRL_ADDR 0x1600 268#define REG_ODPG_CNTRL_OFFS 21 269 270#define REG_PHY_LOCK_MASK_ADDR 0x1670 271#define REG_PHY_LOCK_MASK_MASK 0xfffff000 272 273#define REG_PHY_LOCK_STATUS_ADDR 0x1674 274#define REG_PHY_LOCK_STATUS_LOCK_OFFS 9 275#define REG_PHY_LOCK_STATUS_LOCK_MASK 0xfff 276#define REG_PHY_LOCK_APLL_ADLL_STATUS_MASK 0x7ff 277 278#define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16a0 279#define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR 0xc0000000 280#define REG_PHY_REGISTRY_FILE_ACCESS_OP_RD 0x80000000 281#define REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE 0x80000000 282#define REG_PHY_BC_OFFS 27 283#define REG_PHY_CNTRL_OFFS 26 284#define REG_PHY_CS_OFFS 16 285#define REG_PHY_DQS_REF_DLY_OFFS 10 286#define REG_PHY_PHASE_OFFS 8 287#define REG_PHY_PUP_OFFS 22 288 289#define REG_TRAINING_WL_ADDR 0x16ac 290#define REG_TRAINING_WL_CS_MASK 0xfffffffc 291#define REG_TRAINING_WL_UPD_OFFS 2 292#define REG_TRAINING_WL_CS_DONE_OFFS 3 293#define REG_TRAINING_WL_RATIO_MASK 0xffffff0f 294#define REG_TRAINING_WL_1TO1 0x50 295#define REG_TRAINING_WL_2TO1 0x10 296#define REG_TRAINING_WL_DELAYEXP_MASK 0x20000000 297#define REG_TRAINING_WL_RESULTS_MASK 0x000001ff 298#define REG_TRAINING_WL_RESULTS_OFFS 20 299 300#define REG_REGISTERED_DRAM_CTRL_ADDR 0x16d0 301#define REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS 15 302#define REG_REGISTERED_DRAM_CTRL_PARITY_MASK 0x3f 303 304/* DLB */ 305#define REG_STATIC_DRAM_DLB_CONTROL 0x1700 306#define DLB_BUS_OPTIMIZATION_WEIGHTS_REG 0x1704 307#define DLB_AGING_REGISTER 0x1708 308#define DLB_EVICTION_CONTROL_REG 0x170c 309#define DLB_EVICTION_TIMERS_REGISTER_REG 0x1710 310#define DLB_USER_COMMAND_REG 0x1714 311#define DLB_BUS_WEIGHTS_DIFF_CS 0x1770 312#define DLB_BUS_WEIGHTS_DIFF_BG 0x1774 313#define DLB_BUS_WEIGHTS_SAME_BG 0x1778 314#define DLB_BUS_WEIGHTS_RD_WR 0x177c 315#define DLB_BUS_WEIGHTS_ATTR_SYS_PRIO 0x1780 316#define DLB_MAIN_QUEUE_MAP 0x1784 317#define DLB_LINE_SPLIT 0x1788 318 319#define DLB_ENABLE 0x1 320#define DLB_WRITE_COALESING (0x1 << 2) 321#define DLB_AXI_PREFETCH_EN (0x1 << 3) 322#define DLB_MBUS_PREFETCH_EN (0x1 << 4) 323#define PREFETCH_N_LN_SZ_TR (0x1 << 6) 324#define DLB_INTERJECTION_ENABLE (0x1 << 3) 325 326/* CPU */ 327#define REG_BOOTROM_ROUTINE_ADDR 0x182d0 328#define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12 329 330#define REG_DRAM_INIT_CTRL_STATUS_ADDR 0x18488 331#define REG_DRAM_INIT_CTRL_TRN_CLK_OFFS 16 332#define REG_CPU_DIV_CLK_CTRL_0_NEW_RATIO 0x000200ff 333#define REG_DRAM_INIT_CTRL_STATUS_2_ADDR 0x1488 334 335#define REG_CPU_DIV_CLK_CTRL_0_ADDR 0x18700 336 337#define REG_CPU_DIV_CLK_CTRL_1_ADDR 0x18704 338#define REG_CPU_DIV_CLK_CTRL_2_ADDR 0x18708 339 340#define REG_CPU_DIV_CLK_CTRL_3_ADDR 0x1870c 341#define REG_CPU_DIV_CLK_CTRL_3_FREQ_MASK 0xffffc0ff 342#define REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS 8 343 344#define REG_CPU_DIV_CLK_CTRL_4_ADDR 0x18710 345 346#define REG_CPU_DIV_CLK_STATUS_0_ADDR 0x18718 347#define REG_CPU_DIV_CLK_ALL_STABLE_OFFS 8 348 349#define REG_CPU_PLL_CTRL_0_ADDR 0x1871c 350#define REG_CPU_PLL_STATUS_0_ADDR 0x18724 351#define REG_CORE_DIV_CLK_CTRL_ADDR 0x18740 352#define REG_CORE_DIV_CLK_STATUS_ADDR 0x18744 353#define REG_DDRPHY_APLL_CTRL_ADDR 0x18780 354 355#define REG_DDRPHY_APLL_CTRL_2_ADDR 0x18784 356#define REG_SFABRIC_CLK_CTRL_ADDR 0x20858 357#define REG_SFABRIC_CLK_CTRL_SMPL_OFFS 8 358 359/* DRAM Windows */ 360#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8 361#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040 362#define REG_XBAR_WIN_4_BASE_ADDR 0x20044 363#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048 364#define REG_FASTPATH_WIN_0_CTRL_ADDR 0x20184 365#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078 366 367/* SRAM */ 368#define REG_CDI_CONFIG_ADDR 0x20220 369#define REG_SRAM_WINDOW_0_ADDR 0x20240 370#define REG_SRAM_WINDOW_0_ENA_OFFS 0 371#define REG_SRAM_WINDOW_1_ADDR 0x20244 372#define REG_SRAM_L2_ENA_ADDR 0x8500 373#define REG_SRAM_CLEAN_BY_WAY_ADDR 0x87bc 374 375/* Timers */ 376#define REG_TIMERS_CTRL_ADDR 0x20300 377#define REG_TIMERS_EVENTS_ADDR 0x20304 378#define REG_TIMER0_VALUE_ADDR 0x20314 379#define REG_TIMER1_VALUE_ADDR 0x2031c 380#define REG_TIMER0_ENABLE_MASK 0x1 381 382#define MV_BOARD_REFCLK_25MHZ 25000000 383#define CNTMR_RELOAD_REG(tmr) (REG_TIMERS_CTRL_ADDR + 0x10 + (tmr * 8)) 384#define CNTMR_VAL_REG(tmr) (REG_TIMERS_CTRL_ADDR + 0x14 + (tmr * 8)) 385#define CNTMR_CTRL_REG(tmr) (REG_TIMERS_CTRL_ADDR) 386#define CTCR_ARM_TIMER_EN_OFFS(timer) (timer * 2) 387#define CTCR_ARM_TIMER_EN_MASK(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer)) 388#define CTCR_ARM_TIMER_EN(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer)) 389 390#define CTCR_ARM_TIMER_AUTO_OFFS(timer) (1 + (timer * 2)) 391#define CTCR_ARM_TIMER_AUTO_MASK(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer)) 392#define CTCR_ARM_TIMER_AUTO_EN(timer) (1 << CTCR_ARM_TIMER_AUTO_OFFS(timer)) 393 394/* PMU */ 395#define REG_PMU_I_F_CTRL_ADDR 0x1c090 396#define REG_PMU_DUNIT_BLK_OFFS 16 397#define REG_PMU_DUNIT_RFRS_OFFS 20 398#define REG_PMU_DUNIT_ACK_OFFS 24 399 400/* MBUS */ 401#define MBUS_UNITS_PRIORITY_CONTROL_REG (MBUS_REGS_OFFSET + 0x420) 402#define FABRIC_UNITS_PRIORITY_CONTROL_REG (MBUS_REGS_OFFSET + 0x424) 403#define MBUS_UNITS_PREFETCH_CONTROL_REG (MBUS_REGS_OFFSET + 0x428) 404#define FABRIC_UNITS_PREFETCH_CONTROL_REG (MBUS_REGS_OFFSET + 0x42c) 405 406#define REG_PM_STAT_MASK_ADDR 0x2210c 407#define REG_PM_STAT_MASK_CPU0_IDLE_MASK_OFFS 16 408 409#define REG_PM_EVENT_STAT_MASK_ADDR 0x22120 410#define REG_PM_EVENT_STAT_MASK_DFS_DONE_OFFS 17 411 412#define REG_PM_CTRL_CONFIG_ADDR 0x22104 413#define REG_PM_CTRL_CONFIG_DFS_REQ_OFFS 18 414 415#define REG_FABRIC_LOCAL_IRQ_MASK_ADDR 0x218c4 416#define REG_FABRIC_LOCAL_IRQ_PMU_MASK_OFFS 18 417 418/* Controller revision info */ 419#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 420#define PCCRIR_REVID_OFFS 0 /* Revision ID */ 421#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) 422 423/* Power Management Clock Gating Control Register */ 424#define POWER_MNG_CTRL_REG 0x18220 425#define PEX_DEVICE_AND_VENDOR_ID 0x000 426#define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg)) 427#define PMC_PEXSTOPCLOCK_OFFS(p) ((p) < 8 ? (5 + (p)) : (18 + (p))) 428#define PMC_PEXSTOPCLOCK_MASK(p) (1 << PMC_PEXSTOPCLOCK_OFFS(p)) 429#define PMC_PEXSTOPCLOCK_EN(p) (1 << PMC_PEXSTOPCLOCK_OFFS(p)) 430#define PMC_PEXSTOPCLOCK_STOP(p) (0 << PMC_PEXSTOPCLOCK_OFFS(p)) 431 432/* TWSI */ 433#define TWSI_DATA_ADDR_MASK 0x7 434#define TWSI_DATA_ADDR_OFFS 1 435 436/* General */ 437#define MAX_CS 4 438 439/* Frequencies */ 440#define FAB_OPT 21 441#define CLK_CPU 12 442#define CLK_VCO (2 * CLK_CPU) 443#define CLK_DDR 12 444 445/* CPU Frequencies: */ 446#define CLK_CPU_1000 0 447#define CLK_CPU_1066 1 448#define CLK_CPU_1200 2 449#define CLK_CPU_1333 3 450#define CLK_CPU_1500 4 451#define CLK_CPU_1666 5 452#define CLK_CPU_1800 6 453#define CLK_CPU_2000 7 454#define CLK_CPU_600 8 455#define CLK_CPU_667 9 456#define CLK_CPU_800 0xa 457 458/* Extra Cpu Frequencies: */ 459#define CLK_CPU_1600 11 460#define CLK_CPU_2133 12 461#define CLK_CPU_2200 13 462#define CLK_CPU_2400 14 463 464#endif /* _DDR3_HWS_HW_TRAINING_DEF_H */ 465