uboot/drivers/spi/zynq_qspi.c
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   1/*
   2 * (C) Copyright 2013 Xilinx, Inc.
   3 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
   4 *
   5 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#include <common.h>
  11#include <dm.h>
  12#include <malloc.h>
  13#include <spi.h>
  14#include <asm/io.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18/* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
  19#define ZYNQ_QSPI_CR_IFMODE_MASK        BIT(31) /* Flash intrface mode*/
  20#define ZYNQ_QSPI_CR_MSA_MASK           BIT(15) /* Manual start enb */
  21#define ZYNQ_QSPI_CR_MCS_MASK           BIT(14) /* Manual chip select */
  22#define ZYNQ_QSPI_CR_PCS_MASK           BIT(10) /* Peri chip select */
  23#define ZYNQ_QSPI_CR_FW_MASK            GENMASK(7, 6)   /* FIFO width */
  24#define ZYNQ_QSPI_CR_SS_MASK            GENMASK(13, 10) /* Slave Select */
  25#define ZYNQ_QSPI_CR_BAUD_MASK          GENMASK(5, 3)   /* Baud rate div */
  26#define ZYNQ_QSPI_CR_CPHA_MASK          BIT(2)  /* Clock phase */
  27#define ZYNQ_QSPI_CR_CPOL_MASK          BIT(1)  /* Clock polarity */
  28#define ZYNQ_QSPI_CR_MSTREN_MASK        BIT(0)  /* Mode select */
  29#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK     BIT(4)  /* RX_FIFO_not_empty */
  30#define ZYNQ_QSPI_IXR_TXOW_MASK         BIT(2)  /* TX_FIFO_not_full */
  31#define ZYNQ_QSPI_IXR_ALL_MASK          GENMASK(6, 0)   /* All IXR bits */
  32#define ZYNQ_QSPI_ENR_SPI_EN_MASK       BIT(0)  /* SPI Enable */
  33#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK  BIT(31) /* Linear QSPI Mode */
  34
  35/* zynq qspi Transmit Data Register */
  36#define ZYNQ_QSPI_TXD_00_00_OFFSET      0x1C    /* Transmit 4-byte inst */
  37#define ZYNQ_QSPI_TXD_00_01_OFFSET      0x80    /* Transmit 1-byte inst */
  38#define ZYNQ_QSPI_TXD_00_10_OFFSET      0x84    /* Transmit 2-byte inst */
  39#define ZYNQ_QSPI_TXD_00_11_OFFSET      0x88    /* Transmit 3-byte inst */
  40
  41#define ZYNQ_QSPI_TXFIFO_THRESHOLD      1       /* Tx FIFO threshold level*/
  42#define ZYNQ_QSPI_RXFIFO_THRESHOLD      32      /* Rx FIFO threshold level */
  43
  44#define ZYNQ_QSPI_CR_BAUD_MAX           8       /* Baud rate divisor max val */
  45#define ZYNQ_QSPI_CR_BAUD_SHIFT         3       /* Baud rate divisor shift */
  46#define ZYNQ_QSPI_CR_SS_SHIFT           10      /* Slave select shift */
  47
  48#define ZYNQ_QSPI_FIFO_DEPTH            63
  49#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
  50#define CONFIG_SYS_ZYNQ_QSPI_WAIT       CONFIG_SYS_HZ/100       /* 10 ms */
  51#endif
  52
  53/* zynq qspi register set */
  54struct zynq_qspi_regs {
  55        u32 cr;         /* 0x00 */
  56        u32 isr;        /* 0x04 */
  57        u32 ier;        /* 0x08 */
  58        u32 idr;        /* 0x0C */
  59        u32 imr;        /* 0x10 */
  60        u32 enr;        /* 0x14 */
  61        u32 dr;         /* 0x18 */
  62        u32 txd0r;      /* 0x1C */
  63        u32 drxr;       /* 0x20 */
  64        u32 sicr;       /* 0x24 */
  65        u32 txftr;      /* 0x28 */
  66        u32 rxftr;      /* 0x2C */
  67        u32 gpior;      /* 0x30 */
  68        u32 reserved0[19];
  69        u32 txd1r;      /* 0x80 */
  70        u32 txd2r;      /* 0x84 */
  71        u32 txd3r;      /* 0x88 */
  72        u32 reserved1[5];
  73        u32 lqspicfg;   /* 0xA0 */
  74        u32 lqspists;   /* 0xA4 */
  75};
  76
  77/* zynq qspi platform data */
  78struct zynq_qspi_platdata {
  79        struct zynq_qspi_regs *regs;
  80        u32 frequency;          /* input frequency */
  81        u32 speed_hz;
  82};
  83
  84/* zynq qspi priv */
  85struct zynq_qspi_priv {
  86        struct zynq_qspi_regs *regs;
  87        u8 cs;
  88        u8 mode;
  89        u8 fifo_depth;
  90        u32 freq;               /* required frequency */
  91        const void *tx_buf;
  92        void *rx_buf;
  93        unsigned len;
  94        int bytes_to_transfer;
  95        int bytes_to_receive;
  96        unsigned int is_inst;
  97        unsigned cs_change:1;
  98};
  99
 100static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
 101{
 102        struct zynq_qspi_platdata *plat = bus->platdata;
 103        const void *blob = gd->fdt_blob;
 104        int node = dev_of_offset(bus);
 105
 106        plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
 107                                                              node, "reg");
 108
 109        /* FIXME: Use 166MHz as a suitable default */
 110        plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
 111                                        166666666);
 112        plat->speed_hz = plat->frequency / 2;
 113
 114        debug("%s: regs=%p max-frequency=%d\n", __func__,
 115              plat->regs, plat->frequency);
 116
 117        return 0;
 118}
 119
 120static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
 121{
 122        struct zynq_qspi_regs *regs = priv->regs;
 123        u32 confr;
 124
 125        /* Disable QSPI */
 126        writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
 127
 128        /* Disable Interrupts */
 129        writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
 130
 131        /* Clear the TX and RX threshold reg */
 132        writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, &regs->txftr);
 133        writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, &regs->rxftr);
 134
 135        /* Clear the RX FIFO */
 136        while (readl(&regs->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
 137                readl(&regs->drxr);
 138
 139        /* Clear Interrupts */
 140        writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->isr);
 141
 142        /* Manual slave select and Auto start */
 143        confr = readl(&regs->cr);
 144        confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
 145        confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
 146                ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
 147                ZYNQ_QSPI_CR_MSTREN_MASK;
 148        writel(confr, &regs->cr);
 149
 150        /* Disable the LQSPI feature */
 151        confr = readl(&regs->lqspicfg);
 152        confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
 153        writel(confr, &regs->lqspicfg);
 154
 155        /* Enable SPI */
 156        writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
 157}
 158
 159static int zynq_qspi_probe(struct udevice *bus)
 160{
 161        struct zynq_qspi_platdata *plat = dev_get_platdata(bus);
 162        struct zynq_qspi_priv *priv = dev_get_priv(bus);
 163
 164        priv->regs = plat->regs;
 165        priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
 166
 167        /* init the zynq spi hw */
 168        zynq_qspi_init_hw(priv);
 169
 170        return 0;
 171}
 172
 173/*
 174 * zynq_qspi_read_data - Copy data to RX buffer
 175 * @zqspi:      Pointer to the zynq_qspi structure
 176 * @data:       The 32 bit variable where data is stored
 177 * @size:       Number of bytes to be copied from data to RX buffer
 178 */
 179static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
 180{
 181        u8 byte3;
 182
 183        debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
 184              data, (unsigned)(priv->rx_buf), size);
 185
 186        if (priv->rx_buf) {
 187                switch (size) {
 188                case 1:
 189                        *((u8 *)priv->rx_buf) = data;
 190                        priv->rx_buf += 1;
 191                        break;
 192                case 2:
 193                        *((u16 *)priv->rx_buf) = data;
 194                        priv->rx_buf += 2;
 195                        break;
 196                case 3:
 197                        *((u16 *)priv->rx_buf) = data;
 198                        priv->rx_buf += 2;
 199                        byte3 = (u8)(data >> 16);
 200                        *((u8 *)priv->rx_buf) = byte3;
 201                        priv->rx_buf += 1;
 202                        break;
 203                case 4:
 204                        /* Can not assume word aligned buffer */
 205                        memcpy(priv->rx_buf, &data, size);
 206                        priv->rx_buf += 4;
 207                        break;
 208                default:
 209                        /* This will never execute */
 210                        break;
 211                }
 212        }
 213        priv->bytes_to_receive -= size;
 214        if (priv->bytes_to_receive < 0)
 215                priv->bytes_to_receive = 0;
 216}
 217
 218/*
 219 * zynq_qspi_write_data - Copy data from TX buffer
 220 * @zqspi:      Pointer to the zynq_qspi structure
 221 * @data:       Pointer to the 32 bit variable where data is to be copied
 222 * @size:       Number of bytes to be copied from TX buffer to data
 223 */
 224static void zynq_qspi_write_data(struct  zynq_qspi_priv *priv,
 225                u32 *data, u8 size)
 226{
 227        if (priv->tx_buf) {
 228                switch (size) {
 229                case 1:
 230                        *data = *((u8 *)priv->tx_buf);
 231                        priv->tx_buf += 1;
 232                        *data |= 0xFFFFFF00;
 233                        break;
 234                case 2:
 235                        *data = *((u16 *)priv->tx_buf);
 236                        priv->tx_buf += 2;
 237                        *data |= 0xFFFF0000;
 238                        break;
 239                case 3:
 240                        *data = *((u16 *)priv->tx_buf);
 241                        priv->tx_buf += 2;
 242                        *data |= (*((u8 *)priv->tx_buf) << 16);
 243                        priv->tx_buf += 1;
 244                        *data |= 0xFF000000;
 245                        break;
 246                case 4:
 247                        /* Can not assume word aligned buffer */
 248                        memcpy(data, priv->tx_buf, size);
 249                        priv->tx_buf += 4;
 250                        break;
 251                default:
 252                        /* This will never execute */
 253                        break;
 254                }
 255        } else {
 256                *data = 0;
 257        }
 258
 259        debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
 260              *data, (u32)priv->tx_buf, size);
 261
 262        priv->bytes_to_transfer -= size;
 263        if (priv->bytes_to_transfer < 0)
 264                priv->bytes_to_transfer = 0;
 265}
 266
 267static void zynq_qspi_chipselect(struct  zynq_qspi_priv *priv, int is_on)
 268{
 269        u32 confr;
 270        struct zynq_qspi_regs *regs = priv->regs;
 271
 272        confr = readl(&regs->cr);
 273
 274        if (is_on) {
 275                /* Select the slave */
 276                confr &= ~ZYNQ_QSPI_CR_SS_MASK;
 277                confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
 278                                        ZYNQ_QSPI_CR_SS_MASK;
 279        } else
 280                /* Deselect the slave */
 281                confr |= ZYNQ_QSPI_CR_SS_MASK;
 282
 283        writel(confr, &regs->cr);
 284}
 285
 286/*
 287 * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
 288 * @zqspi:      Pointer to the zynq_qspi structure
 289 */
 290static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
 291{
 292        u32 data = 0;
 293        u32 fifocount = 0;
 294        unsigned len, offset;
 295        struct zynq_qspi_regs *regs = priv->regs;
 296        static const unsigned offsets[4] = {
 297                ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
 298                ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
 299
 300        while ((fifocount < size) &&
 301                        (priv->bytes_to_transfer > 0)) {
 302                if (priv->bytes_to_transfer >= 4) {
 303                        if (priv->tx_buf) {
 304                                memcpy(&data, priv->tx_buf, 4);
 305                                priv->tx_buf += 4;
 306                        } else {
 307                                data = 0;
 308                        }
 309                        writel(data, &regs->txd0r);
 310                        priv->bytes_to_transfer -= 4;
 311                        fifocount++;
 312                } else {
 313                        /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
 314                        if (!(readl(&regs->isr)
 315                                        & ZYNQ_QSPI_IXR_TXOW_MASK) &&
 316                                        !priv->rx_buf)
 317                                return;
 318                        len = priv->bytes_to_transfer;
 319                        zynq_qspi_write_data(priv, &data, len);
 320                        offset = (priv->rx_buf) ? offsets[0] : offsets[len];
 321                        writel(data, &regs->cr + (offset / 4));
 322                }
 323        }
 324}
 325
 326/*
 327 * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
 328 * @zqspi:      Pointer to the zynq_qspi structure
 329 *
 330 * This function handles TX empty and Mode Fault interrupts only.
 331 * On TX empty interrupt this function reads the received data from RX FIFO and
 332 * fills the TX FIFO if there is any data remaining to be transferred.
 333 * On Mode Fault interrupt this function indicates that transfer is completed,
 334 * the SPI subsystem will identify the error as the remaining bytes to be
 335 * transferred is non-zero.
 336 *
 337 * returns:     0 for poll timeout
 338 *              1 transfer operation complete
 339 */
 340static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
 341{
 342        struct zynq_qspi_regs *regs = priv->regs;
 343        u32 rxindex = 0;
 344        u32 rxcount;
 345        u32 status, timeout;
 346
 347        /* Poll until any of the interrupt status bits are set */
 348        timeout = get_timer(0);
 349        do {
 350                status = readl(&regs->isr);
 351        } while ((status == 0) &&
 352                (get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT));
 353
 354        if (status == 0) {
 355                printf("zynq_qspi_irq_poll: Timeout!\n");
 356                return -ETIMEDOUT;
 357        }
 358
 359        writel(status, &regs->isr);
 360
 361        /* Disable all interrupts */
 362        writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
 363        if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
 364            (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
 365                /*
 366                 * This bit is set when Tx FIFO has < THRESHOLD entries. We have
 367                 * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
 368                 * is empty
 369                 */
 370                rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
 371                rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
 372                while ((rxindex < rxcount) &&
 373                                (rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
 374                        /* Read out the data from the RX FIFO */
 375                        u32 data;
 376                        data = readl(&regs->drxr);
 377
 378                        if (priv->bytes_to_receive >= 4) {
 379                                if (priv->rx_buf) {
 380                                        memcpy(priv->rx_buf, &data, 4);
 381                                        priv->rx_buf += 4;
 382                                }
 383                                priv->bytes_to_receive -= 4;
 384                        } else {
 385                                zynq_qspi_read_data(priv, data,
 386                                                    priv->bytes_to_receive);
 387                        }
 388                        rxindex++;
 389                }
 390
 391                if (priv->bytes_to_transfer) {
 392                        /* There is more data to send */
 393                        zynq_qspi_fill_tx_fifo(priv,
 394                                               ZYNQ_QSPI_RXFIFO_THRESHOLD);
 395
 396                        writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
 397                } else {
 398                        /*
 399                         * If transfer and receive is completed then only send
 400                         * complete signal
 401                         */
 402                        if (!priv->bytes_to_receive) {
 403                                /* return operation complete */
 404                                writel(ZYNQ_QSPI_IXR_ALL_MASK,
 405                                       &regs->idr);
 406                                return 1;
 407                        }
 408                }
 409        }
 410
 411        return 0;
 412}
 413
 414/*
 415 * zynq_qspi_start_transfer - Initiates the QSPI transfer
 416 * @qspi:       Pointer to the spi_device structure
 417 * @transfer:   Pointer to the spi_transfer structure which provide information
 418 *              about next transfer parameters
 419 *
 420 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
 421 * transfer to be completed.
 422 *
 423 * returns:     Number of bytes transferred in the last transfer
 424 */
 425static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
 426{
 427        u32 data = 0;
 428        struct zynq_qspi_regs *regs = priv->regs;
 429
 430        debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
 431              (u32)priv, (u32)priv, priv->len);
 432
 433        priv->bytes_to_transfer = priv->len;
 434        priv->bytes_to_receive = priv->len;
 435
 436        if (priv->len < 4)
 437                zynq_qspi_fill_tx_fifo(priv, priv->len);
 438        else
 439                zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
 440
 441        writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
 442
 443        /* wait for completion */
 444        do {
 445                data = zynq_qspi_irq_poll(priv);
 446        } while (data == 0);
 447
 448        return (priv->len) - (priv->bytes_to_transfer);
 449}
 450
 451static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
 452{
 453        unsigned cs_change = 1;
 454        int status = 0;
 455
 456        while (1) {
 457                /* Select the chip if required */
 458                if (cs_change)
 459                        zynq_qspi_chipselect(priv, 1);
 460
 461                cs_change = priv->cs_change;
 462
 463                if (!priv->tx_buf && !priv->rx_buf && priv->len) {
 464                        status = -1;
 465                        break;
 466                }
 467
 468                /* Request the transfer */
 469                if (priv->len) {
 470                        status = zynq_qspi_start_transfer(priv);
 471                        priv->is_inst = 0;
 472                }
 473
 474                if (status != priv->len) {
 475                        if (status > 0)
 476                                status = -EMSGSIZE;
 477                        debug("zynq_qspi_transfer:%d len:%d\n",
 478                              status, priv->len);
 479                        break;
 480                }
 481                status = 0;
 482
 483                if (cs_change)
 484                        /* Deselect the chip */
 485                        zynq_qspi_chipselect(priv, 0);
 486
 487                break;
 488        }
 489
 490        return 0;
 491}
 492
 493static int zynq_qspi_claim_bus(struct udevice *dev)
 494{
 495        struct udevice *bus = dev->parent;
 496        struct zynq_qspi_priv *priv = dev_get_priv(bus);
 497        struct zynq_qspi_regs *regs = priv->regs;
 498
 499        writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
 500
 501        return 0;
 502}
 503
 504static int zynq_qspi_release_bus(struct udevice *dev)
 505{
 506        struct udevice *bus = dev->parent;
 507        struct zynq_qspi_priv *priv = dev_get_priv(bus);
 508        struct zynq_qspi_regs *regs = priv->regs;
 509
 510        writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
 511
 512        return 0;
 513}
 514
 515static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 516                const void *dout, void *din, unsigned long flags)
 517{
 518        struct udevice *bus = dev->parent;
 519        struct zynq_qspi_priv *priv = dev_get_priv(bus);
 520        struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 521
 522        priv->cs = slave_plat->cs;
 523        priv->tx_buf = dout;
 524        priv->rx_buf = din;
 525        priv->len = bitlen / 8;
 526
 527        debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
 528              bus->seq, slave_plat->cs, bitlen, priv->len, flags);
 529
 530        /*
 531         * Festering sore.
 532         * Assume that the beginning of a transfer with bits to
 533         * transmit must contain a device command.
 534         */
 535        if (dout && flags & SPI_XFER_BEGIN)
 536                priv->is_inst = 1;
 537        else
 538                priv->is_inst = 0;
 539
 540        if (flags & SPI_XFER_END)
 541                priv->cs_change = 1;
 542        else
 543                priv->cs_change = 0;
 544
 545        zynq_qspi_transfer(priv);
 546
 547        return 0;
 548}
 549
 550static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
 551{
 552        struct zynq_qspi_platdata *plat = bus->platdata;
 553        struct zynq_qspi_priv *priv = dev_get_priv(bus);
 554        struct zynq_qspi_regs *regs = priv->regs;
 555        uint32_t confr;
 556        u8 baud_rate_val = 0;
 557
 558        if (speed > plat->frequency)
 559                speed = plat->frequency;
 560
 561        /* Set the clock frequency */
 562        confr = readl(&regs->cr);
 563        if (speed == 0) {
 564                /* Set baudrate x8, if the freq is 0 */
 565                baud_rate_val = 0x2;
 566        } else if (plat->speed_hz != speed) {
 567                while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
 568                       ((plat->frequency /
 569                       (2 << baud_rate_val)) > speed))
 570                        baud_rate_val++;
 571
 572                plat->speed_hz = speed / (2 << baud_rate_val);
 573        }
 574        confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
 575        confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
 576
 577        writel(confr, &regs->cr);
 578        priv->freq = speed;
 579
 580        debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
 581
 582        return 0;
 583}
 584
 585static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
 586{
 587        struct zynq_qspi_priv *priv = dev_get_priv(bus);
 588        struct zynq_qspi_regs *regs = priv->regs;
 589        uint32_t confr;
 590
 591        /* Set the SPI Clock phase and polarities */
 592        confr = readl(&regs->cr);
 593        confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
 594
 595        if (mode & SPI_CPHA)
 596                confr |= ZYNQ_QSPI_CR_CPHA_MASK;
 597        if (mode & SPI_CPOL)
 598                confr |= ZYNQ_QSPI_CR_CPOL_MASK;
 599
 600        writel(confr, &regs->cr);
 601        priv->mode = mode;
 602
 603        debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
 604
 605        return 0;
 606}
 607
 608static const struct dm_spi_ops zynq_qspi_ops = {
 609        .claim_bus      = zynq_qspi_claim_bus,
 610        .release_bus    = zynq_qspi_release_bus,
 611        .xfer           = zynq_qspi_xfer,
 612        .set_speed      = zynq_qspi_set_speed,
 613        .set_mode       = zynq_qspi_set_mode,
 614};
 615
 616static const struct udevice_id zynq_qspi_ids[] = {
 617        { .compatible = "xlnx,zynq-qspi-1.0" },
 618        { }
 619};
 620
 621U_BOOT_DRIVER(zynq_qspi) = {
 622        .name   = "zynq_qspi",
 623        .id     = UCLASS_SPI,
 624        .of_match = zynq_qspi_ids,
 625        .ops    = &zynq_qspi_ops,
 626        .ofdata_to_platdata = zynq_qspi_ofdata_to_platdata,
 627        .platdata_auto_alloc_size = sizeof(struct zynq_qspi_platdata),
 628        .priv_auto_alloc_size = sizeof(struct zynq_qspi_priv),
 629        .probe  = zynq_qspi_probe,
 630};
 631