1/* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * Hayden Fraser (Hayden.Fraser@freescale.com) 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef _M5253EVBE_H 9#define _M5253EVBE_H 10 11#define CONFIG_M5253EVBE /* define board type */ 12 13#define CONFIG_MCFTMR 14 15#define CONFIG_MCFUART 16#define CONFIG_SYS_UART_PORT (0) 17 18#undef CONFIG_WATCHDOG /* disable watchdog */ 19 20 21/* Configuration for environment 22 * Environment is embedded in u-boot in the second sector of the flash 23 */ 24#ifndef CONFIG_MONITOR_IS_IN_RAM 25#define CONFIG_ENV_OFFSET 0x4000 26#define CONFIG_ENV_SECT_SIZE 0x2000 27#define CONFIG_ENV_IS_IN_FLASH 1 28#else 29#define CONFIG_ENV_ADDR 0xffe04000 30#define CONFIG_ENV_SECT_SIZE 0x2000 31#define CONFIG_ENV_IS_IN_FLASH 1 32#endif 33 34#define LDS_BOARD_TEXT \ 35 . = DEFINED(env_offset) ? env_offset : .; \ 36 common/env_embedded.o (.text) 37 38/* 39 * BOOTP options 40 */ 41#undef CONFIG_BOOTP_BOOTFILESIZE 42#undef CONFIG_BOOTP_BOOTPATH 43#undef CONFIG_BOOTP_GATEWAY 44#undef CONFIG_BOOTP_HOSTNAME 45 46/* 47 * Command line configuration. 48 */ 49 50/* ATA */ 51#define CONFIG_IDE_RESET 1 52#define CONFIG_IDE_PREINIT 1 53#define CONFIG_ATAPI 54#undef CONFIG_LBA48 55 56#define CONFIG_SYS_IDE_MAXBUS 1 57#define CONFIG_SYS_IDE_MAXDEVICE 2 58 59#define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 60#define CONFIG_SYS_ATA_IDE0_OFFSET 0 61 62#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 63#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 64#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 65#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 66 67#define CONFIG_SYS_LONGHELP /* undef to save memory */ 68 69#if defined(CONFIG_CMD_KGDB) 70#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 71#else 72#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 73#endif 74#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 75#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 76#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 77 78#define CONFIG_SYS_LOAD_ADDR 0x00100000 79 80#define CONFIG_SYS_MEMTEST_START 0x400 81#define CONFIG_SYS_MEMTEST_END 0x380000 82 83#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 84#define CONFIG_SYS_FAST_CLK 85#ifdef CONFIG_SYS_FAST_CLK 86# define CONFIG_SYS_PLLCR 0x1243E054 87# define CONFIG_SYS_CLK 140000000 88#else 89# define CONFIG_SYS_PLLCR 0x135a4140 90# define CONFIG_SYS_CLK 70000000 91#endif 92 93/* 94 * Low Level Configuration Settings 95 * (address mappings, register initial values, etc.) 96 * You should know what you are doing if you make changes here. 97 */ 98 99#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 100#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 101 102/* 103 * Definitions for initial stack pointer and data area (in DPRAM) 104 */ 105#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 106#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 107#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 108#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 109 110/* 111 * Start addresses for the final memory configuration 112 * (Set up by the startup code) 113 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 114 */ 115#define CONFIG_SYS_SDRAM_BASE 0x00000000 116#define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */ 117 118#ifdef CONFIG_MONITOR_IS_IN_RAM 119#define CONFIG_SYS_MONITOR_BASE 0x20000 120#else 121#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 122#endif 123 124#define CONFIG_SYS_MONITOR_LEN 0x40000 125#define CONFIG_SYS_MALLOC_LEN (256 << 10) 126#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 127 128/* 129 * For booting Linux, the board info and command line data 130 * have to be in the first 8 MB of memory, since this is 131 * the maximum mapped by the Linux kernel during initialization ?? 132 */ 133#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 134#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 135 136/* FLASH organization */ 137#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 138#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 139#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ 140#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 141 142#define CONFIG_SYS_FLASH_CFI 1 143#define CONFIG_FLASH_CFI_DRIVER 1 144#define CONFIG_SYS_FLASH_SIZE 0x200000 145#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 146 147/* Cache Configuration */ 148#define CONFIG_SYS_CACHELINE_SIZE 16 149 150#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 151 CONFIG_SYS_INIT_RAM_SIZE - 8) 152#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 153 CONFIG_SYS_INIT_RAM_SIZE - 4) 154#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 155#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 156 CF_ADDRMASK(2) | \ 157 CF_ACR_EN | CF_ACR_SM_ALL) 158#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 159 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 160 CF_ACR_EN | CF_ACR_SM_ALL) 161#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 162 CF_CACR_DBWE) 163 164/* Port configuration */ 165#define CONFIG_SYS_FECI2C 0xF0 166 167#define CONFIG_SYS_CS0_BASE 0xFFE00000 168#define CONFIG_SYS_CS0_MASK 0x001F0021 169#define CONFIG_SYS_CS0_CTRL 0x00001D80 170 171/*----------------------------------------------------------------------- 172 * Port configuration 173 */ 174#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 175#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 176#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 177#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 178#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 179#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 180#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 181 182#endif /* _M5253EVB_H */ 183