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8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12
13
14
15#define CONFIG_E300 1
16#define CONFIG_QE 1
17#define CONFIG_MPC832x 1
18
19#define CONFIG_SYS_TEXT_BASE 0xFE000000
20
21
22
23
24#define CONFIG_83XX_CLKIN 66666667
25
26#ifndef CONFIG_SYS_CLK_FREQ
27#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
28#endif
29
30
31
32
33#define CONFIG_SYS_HRCW_LOW (\
34 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
35 HRCWL_DDR_TO_SCB_CLK_2X1 |\
36 HRCWL_VCO_1X2 |\
37 HRCWL_CSB_TO_CLKIN_2X1 |\
38 HRCWL_CORE_TO_CSB_2_5X1 |\
39 HRCWL_CE_PLL_VCO_DIV_2 |\
40 HRCWL_CE_PLL_DIV_1X1 |\
41 HRCWL_CE_TO_PLL_1X3)
42
43#define CONFIG_SYS_HRCW_HIGH (\
44 HRCWH_PCI_HOST |\
45 HRCWH_PCI1_ARBITER_ENABLE |\
46 HRCWH_CORE_ENABLE |\
47 HRCWH_FROM_0X00000100 |\
48 HRCWH_BOOTSEQ_DISABLE |\
49 HRCWH_SW_WATCHDOG_DISABLE |\
50 HRCWH_ROM_LOC_LOCAL_16BIT |\
51 HRCWH_BIG_ENDIAN |\
52 HRCWH_LALE_NORMAL)
53
54
55
56
57#define CONFIG_SYS_SICRL 0x00000000
58
59
60
61
62#define CONFIG_SYS_IMMR 0xE0000000
63
64
65
66
67#define CONFIG_SYS_ACR_PIPE_DEP 3
68#define CONFIG_SYS_ACR_RPTCNT 3
69
70#define CONFIG_SYS_SPCR_OPT 1
71
72
73
74
75#define CONFIG_SYS_DDR_BASE 0x00000000
76#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
77#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
78
79#undef CONFIG_SPD_EEPROM
80#if defined(CONFIG_SPD_EEPROM)
81
82
83#define SPD_EEPROM_ADDRESS 0x51
84#else
85
86
87#define CONFIG_SYS_DDR_SIZE 64
88#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
89 | CSCONFIG_ROW_BIT_13 \
90 | CSCONFIG_COL_BIT_9)
91
92#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
93 | (0 << TIMING_CFG0_WRT_SHIFT) \
94 | (0 << TIMING_CFG0_RRT_SHIFT) \
95 | (0 << TIMING_CFG0_WWT_SHIFT) \
96 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
97 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
98 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
99 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
100
101#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
102 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
103 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
104 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
105 | (3 << TIMING_CFG1_REFREC_SHIFT) \
106 | (2 << TIMING_CFG1_WRREC_SHIFT) \
107 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
108 | (2 << TIMING_CFG1_WRTORD_SHIFT))
109
110#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
111 | (31 << TIMING_CFG2_CPO_SHIFT) \
112 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
113 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
114 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
115 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
116 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
117
118#define CONFIG_SYS_DDR_TIMING_3 0x00000000
119#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
120
121#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
122 | (0x0232 << SDRAM_MODE_SD_SHIFT))
123
124#define CONFIG_SYS_DDR_MODE2 0x8000c000
125#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
126 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
127
128#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
129#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
130 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
131 | SDRAM_CFG_32_BE)
132
133#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
134#endif
135
136
137
138
139#undef CONFIG_SYS_DRAM_TEST
140#define CONFIG_SYS_MEMTEST_START 0x00030000
141#define CONFIG_SYS_MEMTEST_END 0x03f00000
142
143
144
145
146#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
147
148#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
149#define CONFIG_SYS_RAMBOOT
150#else
151#undef CONFIG_SYS_RAMBOOT
152#endif
153
154
155#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
156#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
157
158
159
160
161#define CONFIG_SYS_INIT_RAM_LOCK 1
162#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
163#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
164#define CONFIG_SYS_GBL_DATA_OFFSET \
165 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
166
167
168
169
170#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
171#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
172#define CONFIG_SYS_LBC_LBCR 0x00000000
173
174
175
176
177#define CONFIG_SYS_FLASH_CFI
178#define CONFIG_FLASH_CFI_DRIVER
179#define CONFIG_SYS_FLASH_BASE 0xFE000000
180#define CONFIG_SYS_FLASH_SIZE 16
181#define CONFIG_SYS_FLASH_PROTECTION 1
182
183
184#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
185#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
186
187#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
188 | BR_PS_16 \
189 | BR_MS_GPCM \
190 | BR_V)
191#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
192 | OR_GPCM_XAM \
193 | OR_GPCM_CSNT \
194 | OR_GPCM_ACS_DIV2 \
195 | OR_GPCM_XACS \
196 | OR_GPCM_SCY_15 \
197 | OR_GPCM_TRLX_SET \
198 | OR_GPCM_EHTR_SET \
199 | OR_GPCM_EAD)
200
201
202#define CONFIG_SYS_MAX_FLASH_BANKS 1
203#define CONFIG_SYS_MAX_FLASH_SECT 128
204
205#undef CONFIG_SYS_FLASH_CHECKSUM
206
207
208
209
210#define CONFIG_CONS_INDEX 1
211#define CONFIG_SYS_NS16550_SERIAL
212#define CONFIG_SYS_NS16550_REG_SIZE 1
213#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
214
215#define CONFIG_SYS_BAUDRATE_TABLE \
216 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
217
218#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
219#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
220
221#define CONFIG_CMDLINE_EDITING 1
222#define CONFIG_AUTO_COMPLETE
223
224
225#define CONFIG_SYS_I2C
226#define CONFIG_SYS_I2C_FSL
227#define CONFIG_SYS_FSL_I2C_SPEED 400000
228#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
229#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
230#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
231
232
233
234
235#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
236#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
237#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
238#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
239
240
241
242
243
244#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
245#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
246#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
247#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
248#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
249#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
250#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
251#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
252#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000
253
254#ifdef CONFIG_PCI
255#define CONFIG_PCI_INDIRECT_BRIDGE
256#define CONFIG_PCI_SKIP_HOST_BRIDGE
257
258#undef CONFIG_EEPRO100
259#undef CONFIG_PCI_SCAN_SHOW
260#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
261
262#endif
263
264
265
266
267#define CONFIG_UEC_ETH
268#define CONFIG_ETHPRIME "UEC0"
269
270#define CONFIG_UEC_ETH1
271
272#ifdef CONFIG_UEC_ETH1
273#define CONFIG_SYS_UEC1_UCC_NUM 2
274#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
275#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
276#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
277#define CONFIG_SYS_UEC1_PHY_ADDR 4
278#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
279#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
280#endif
281
282#define CONFIG_UEC_ETH2
283
284#ifdef CONFIG_UEC_ETH2
285#define CONFIG_SYS_UEC2_UCC_NUM 1
286#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
287#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
288#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
289#define CONFIG_SYS_UEC2_PHY_ADDR 0
290#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
291#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
292#endif
293
294
295
296
297#ifndef CONFIG_SYS_RAMBOOT
298 #define CONFIG_ENV_IS_IN_FLASH 1
299 #define CONFIG_ENV_ADDR \
300 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
301 #define CONFIG_ENV_SECT_SIZE 0x20000
302 #define CONFIG_ENV_SIZE 0x2000
303#else
304 #define CONFIG_ENV_IS_NOWHERE 1
305 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
306 #define CONFIG_ENV_SIZE 0x2000
307#endif
308
309#define CONFIG_LOADS_ECHO 1
310#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
311
312
313
314
315#define CONFIG_BOOTP_BOOTFILESIZE
316#define CONFIG_BOOTP_BOOTPATH
317#define CONFIG_BOOTP_GATEWAY
318#define CONFIG_BOOTP_HOSTNAME
319
320
321
322
323
324#if defined(CONFIG_PCI)
325 #define CONFIG_CMD_PCI
326#endif
327
328#undef CONFIG_WATCHDOG
329
330
331
332
333#define CONFIG_SYS_LONGHELP
334#define CONFIG_SYS_LOAD_ADDR 0x2000000
335
336#if (CONFIG_CMD_KGDB)
337 #define CONFIG_SYS_CBSIZE 1024
338#else
339 #define CONFIG_SYS_CBSIZE 256
340#endif
341
342
343#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
344#define CONFIG_SYS_MAXARGS 16
345
346#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
347
348
349
350
351
352
353
354#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
355#define CONFIG_SYS_BOOTM_LEN (64 << 20)
356
357
358
359
360#define CONFIG_SYS_HID0_INIT 0x000000000
361#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
362 HID0_ENABLE_INSTRUCTION_CACHE)
363#define CONFIG_SYS_HID2 HID2_HBE
364
365
366
367
368#define CONFIG_HIGH_BATS 1
369
370
371#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
372 | BATL_PP_RW \
373 | BATL_MEMCOHERENCE)
374#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
375 | BATU_BL_256M \
376 | BATU_VS \
377 | BATU_VP)
378#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
379#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
380
381
382#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
383 | BATL_PP_RW \
384 | BATL_CACHEINHIBIT \
385 | BATL_GUARDEDSTORAGE)
386#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
387 | BATU_BL_4M \
388 | BATU_VS \
389 | BATU_VP)
390#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
391#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
392
393
394#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
395 | BATL_PP_RW \
396 | BATL_MEMCOHERENCE)
397#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
398 | BATU_BL_32M \
399 | BATU_VS \
400 | BATU_VP)
401#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
402 | BATL_PP_RW \
403 | BATL_CACHEINHIBIT \
404 | BATL_GUARDEDSTORAGE)
405#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
406
407#define CONFIG_SYS_IBAT3L (0)
408#define CONFIG_SYS_IBAT3U (0)
409#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
410#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
411
412
413#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
414#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
415 | BATU_BL_128K \
416 | BATU_VS \
417 | BATU_VP)
418#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
419#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
420
421#ifdef CONFIG_PCI
422
423#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
424 | BATL_PP_RW \
425 | BATL_MEMCOHERENCE)
426#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
427 | BATU_BL_256M \
428 | BATU_VS \
429 | BATU_VP)
430#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
431#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
432
433#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
434 | BATL_PP_RW \
435 | BATL_CACHEINHIBIT \
436 | BATL_GUARDEDSTORAGE)
437#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
438 | BATU_BL_256M \
439 | BATU_VS \
440 | BATU_VP)
441#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
442#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
443#else
444#define CONFIG_SYS_IBAT5L (0)
445#define CONFIG_SYS_IBAT5U (0)
446#define CONFIG_SYS_IBAT6L (0)
447#define CONFIG_SYS_IBAT6U (0)
448#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
449#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
450#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
451#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
452#endif
453
454
455#define CONFIG_SYS_IBAT7L (0)
456#define CONFIG_SYS_IBAT7U (0)
457#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
458#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
459
460#if (CONFIG_CMD_KGDB)
461#define CONFIG_KGDB_BAUDRATE 230400
462#endif
463
464
465
466
467#define CONFIG_ENV_OVERWRITE
468
469#define CONFIG_HAS_ETH0
470#define CONFIG_HAS_ETH1
471
472
473
474
475#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
476
477#define CONFIG_NETDEV "eth1"
478
479#define CONFIG_HOSTNAME mpc8323erdb
480#define CONFIG_ROOTPATH "/nfsroot"
481#define CONFIG_BOOTFILE "uImage"
482
483#define CONFIG_UBOOTPATH "u-boot.bin"
484#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
485#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
486
487
488#define CONFIG_LOADADDR 800000
489
490#define CONFIG_EXTRA_ENV_SETTINGS \
491 "netdev=" CONFIG_NETDEV "\0" \
492 "uboot=" CONFIG_UBOOTPATH "\0" \
493 "tftpflash=tftp $loadaddr $uboot;" \
494 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
495 " +$filesize; " \
496 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
497 " +$filesize; " \
498 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
499 " $filesize; " \
500 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
501 " +$filesize; " \
502 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
503 " $filesize\0" \
504 "fdtaddr=780000\0" \
505 "fdtfile=" CONFIG_FDTFILE "\0" \
506 "ramdiskaddr=1000000\0" \
507 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
508 "console=ttyS0\0" \
509 "setbootargs=setenv bootargs " \
510 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
511 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
512 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
513 "$netdev:off "\
514 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
515
516#define CONFIG_NFSBOOTCOMMAND \
517 "setenv rootdev /dev/nfs;" \
518 "run setbootargs;" \
519 "run setipargs;" \
520 "tftp $loadaddr $bootfile;" \
521 "tftp $fdtaddr $fdtfile;" \
522 "bootm $loadaddr - $fdtaddr"
523
524#define CONFIG_RAMBOOTCOMMAND \
525 "setenv rootdev /dev/ram;" \
526 "run setbootargs;" \
527 "tftp $ramdiskaddr $ramdiskfile;" \
528 "tftp $loadaddr $bootfile;" \
529 "tftp $fdtaddr $fdtfile;" \
530 "bootm $loadaddr $ramdiskaddr $fdtaddr"
531
532#endif
533