1
2
3
4
5
6
7
8
9
10
11
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16
17
18
19#define CONFIG_E300 1
20#define CONFIG_MPC834x 1
21#define CONFIG_MPC8349 1
22#define CONFIG_MPC8349EMDS 1
23
24#define CONFIG_SYS_TEXT_BASE 0xFE000000
25
26#define CONFIG_PCI_66M
27#ifdef CONFIG_PCI_66M
28#define CONFIG_83XX_CLKIN 66000000
29#else
30#define CONFIG_83XX_CLKIN 33000000
31#endif
32
33#ifdef CONFIG_PCISLAVE
34#define CONFIG_83XX_PCICLK 66666666
35#endif
36
37#ifndef CONFIG_SYS_CLK_FREQ
38#ifdef CONFIG_PCI_66M
39#define CONFIG_SYS_CLK_FREQ 66000000
40#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
41#else
42#define CONFIG_SYS_CLK_FREQ 33000000
43#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
44#endif
45#endif
46
47#define CONFIG_SYS_IMMR 0xE0000000
48
49#undef CONFIG_SYS_DRAM_TEST
50#define CONFIG_SYS_MEMTEST_START 0x00000000
51#define CONFIG_SYS_MEMTEST_END 0x00100000
52
53
54
55
56#define CONFIG_DDR_ECC
57#define CONFIG_DDR_ECC_CMD
58#define CONFIG_SPD_EEPROM
59
60
61
62
63
64#define CONFIG_SYS_SPD_BUS_NUM 0
65#define SPD_EEPROM_ADDRESS1 0x52
66#define SPD_EEPROM_ADDRESS2 0x51
67#define CONFIG_DIMM_SLOTS_PER_CTLR 2
68#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
69#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
70#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
71
72
73
74
75
76
77
78
79
80
81
82#undef CONFIG_DDR_32BIT
83
84#define CONFIG_SYS_DDR_BASE 0x00000000
85#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
86#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
87#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
88 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
89#undef CONFIG_DDR_2T_TIMING
90
91
92
93
94#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
95
96#if defined(CONFIG_SPD_EEPROM)
97
98
99
100#define SPD_EEPROM_ADDRESS 0x51
101#else
102
103
104
105#define CONFIG_SYS_DDR_SIZE 256
106#if defined(CONFIG_DDR_II)
107#define CONFIG_SYS_DDRCDR 0x80080001
108#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
109#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
110#define CONFIG_SYS_DDR_TIMING_0 0x00220802
111#define CONFIG_SYS_DDR_TIMING_1 0x38357322
112#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
113#define CONFIG_SYS_DDR_TIMING_3 0x00000000
114#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
115#define CONFIG_SYS_DDR_MODE 0x47d00432
116#define CONFIG_SYS_DDR_MODE2 0x8000c000
117#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
118#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
119#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
120#else
121#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
122 | CSCONFIG_ROW_BIT_13 \
123 | CSCONFIG_COL_BIT_10)
124#define CONFIG_SYS_DDR_TIMING_1 0x36332321
125#define CONFIG_SYS_DDR_TIMING_2 0x00000800
126#define CONFIG_SYS_DDR_CONTROL 0xc2000000
127#define CONFIG_SYS_DDR_INTERVAL 0x04060100
128
129#if defined(CONFIG_DDR_32BIT)
130
131
132#define CONFIG_SYS_DDR_MODE 0x00000023
133#else
134
135
136#define CONFIG_SYS_DDR_MODE 0x00000022
137#endif
138#endif
139#endif
140
141
142
143
144#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000
145#define CONFIG_SYS_LBC_SDRAM_SIZE 64
146
147
148
149
150#define CONFIG_SYS_FLASH_CFI
151#define CONFIG_FLASH_CFI_DRIVER
152#define CONFIG_SYS_FLASH_BASE 0xFE000000
153#define CONFIG_SYS_FLASH_SIZE 32
154#define CONFIG_SYS_FLASH_PROTECTION 1
155
156
157#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
158 | BR_PS_16 \
159 | BR_MS_GPCM \
160 | BR_V)
161#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
162 | OR_UPM_XAM \
163 | OR_GPCM_CSNT \
164 | OR_GPCM_ACS_DIV2 \
165 | OR_GPCM_XACS \
166 | OR_GPCM_SCY_15 \
167 | OR_GPCM_TRLX_SET \
168 | OR_GPCM_EHTR_SET \
169 | OR_GPCM_EAD)
170
171
172#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
173#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
174
175#define CONFIG_SYS_MAX_FLASH_BANKS 1
176#define CONFIG_SYS_MAX_FLASH_SECT 256
177
178#undef CONFIG_SYS_FLASH_CHECKSUM
179#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
180#define CONFIG_SYS_FLASH_WRITE_TOUT 500
181
182#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
183
184#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
185#define CONFIG_SYS_RAMBOOT
186#else
187#undef CONFIG_SYS_RAMBOOT
188#endif
189
190
191
192
193#define CONFIG_SYS_BCSR 0xE2400000
194
195#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
196#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
197#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
198 | BR_PS_8 \
199 | BR_MS_GPCM \
200 | BR_V)
201
202#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
203 | OR_GPCM_XAM \
204 | OR_GPCM_CSNT \
205 | OR_GPCM_SCY_15 \
206 | OR_GPCM_TRLX_CLEAR \
207 | OR_GPCM_EHTR_CLEAR)
208
209
210#define CONFIG_SYS_INIT_RAM_LOCK 1
211#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
212#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
213
214#define CONFIG_SYS_GBL_DATA_OFFSET \
215 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
216#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
217
218#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
219#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
220
221
222
223
224
225
226
227#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
228#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
229#define CONFIG_SYS_LBC_LBCR 0x00000000
230
231
232
233
234
235#undef CONFIG_SYS_LB_SDRAM
236
237#ifdef CONFIG_SYS_LB_SDRAM
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
255 | BR_PS_32 \
256 | BR_MS_SDRAM \
257 | BR_V)
258
259#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
260#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
277 | OR_SDRAM_XAM \
278 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
279 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
280 | OR_SDRAM_EAD)
281
282
283
284#define CONFIG_SYS_LBC_LSRT 0x32000000
285
286#define CONFIG_SYS_LBC_MRTPR 0x20000000
287
288#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
289 | LSDMR_BSMA1516 \
290 | LSDMR_RFCR8 \
291 | LSDMR_PRETOACT6 \
292 | LSDMR_ACTTORW3 \
293 | LSDMR_BL8 \
294 | LSDMR_WRC3 \
295 | LSDMR_CL3)
296
297
298
299
300#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
301#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
302#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
303#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
304#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
305#endif
306
307
308
309
310#define CONFIG_CONS_INDEX 1
311#define CONFIG_SYS_NS16550_SERIAL
312#define CONFIG_SYS_NS16550_REG_SIZE 1
313#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
314
315#define CONFIG_SYS_BAUDRATE_TABLE \
316 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
317
318#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
319#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
320
321#define CONFIG_CMDLINE_EDITING 1
322#define CONFIG_AUTO_COMPLETE
323
324
325#define CONFIG_SYS_I2C
326#define CONFIG_SYS_I2C_FSL
327#define CONFIG_SYS_FSL_I2C_SPEED 400000
328#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
329#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
330#define CONFIG_SYS_FSL_I2C2_SPEED 400000
331#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
332#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
333#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
334
335
336#define CONFIG_MPC8XXX_SPI
337#undef CONFIG_SOFT_SPI
338
339
340#define CONFIG_SYS_GPIO1_PRELIM
341#define CONFIG_SYS_GPIO1_DIR 0xC0000000
342#define CONFIG_SYS_GPIO1_DAT 0xC0000000
343
344
345#define CONFIG_SYS_TSEC1_OFFSET 0x24000
346#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
347#define CONFIG_SYS_TSEC2_OFFSET 0x25000
348#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
349
350
351#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1
352
353
354
355
356
357#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
358#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
359#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
360#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
361#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
362#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
363#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
364#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
365#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
366
367#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
368#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
369#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
370#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
371#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
372#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
373#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
374#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
375#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
376
377#if defined(CONFIG_PCI)
378
379#define PCI_ONE_PCI1
380#if defined(PCI_64BIT)
381#undef PCI_ALL_PCI1
382#undef PCI_TWO_PCI1
383#undef PCI_ONE_PCI1
384#endif
385
386#define CONFIG_83XX_PCI_STREAMING
387
388#undef CONFIG_EEPRO100
389#undef CONFIG_TULIP
390
391#if !defined(CONFIG_PCI_PNP)
392 #define PCI_ENET0_IOADDR 0xFIXME
393 #define PCI_ENET0_MEMADDR 0xFIXME
394 #define PCI_IDSEL_NUMBER 0x0c
395#endif
396
397#undef CONFIG_PCI_SCAN_SHOW
398#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
399
400#endif
401
402
403
404
405#define CONFIG_TSEC_ENET
406
407#if defined(CONFIG_TSEC_ENET)
408
409#define CONFIG_GMII 1
410#define CONFIG_TSEC1 1
411#define CONFIG_TSEC1_NAME "TSEC0"
412#define CONFIG_TSEC2 1
413#define CONFIG_TSEC2_NAME "TSEC1"
414#define TSEC1_PHY_ADDR 0
415#define TSEC2_PHY_ADDR 1
416#define TSEC1_PHYIDX 0
417#define TSEC2_PHYIDX 0
418#define TSEC1_FLAGS TSEC_GIGABIT
419#define TSEC2_FLAGS TSEC_GIGABIT
420
421
422#define CONFIG_ETHPRIME "TSEC0"
423
424#endif
425
426
427
428
429#define CONFIG_RTC_DS1374
430#define CONFIG_SYS_I2C_RTC_ADDR 0x68
431
432
433
434
435#ifndef CONFIG_SYS_RAMBOOT
436 #define CONFIG_ENV_IS_IN_FLASH 1
437 #define CONFIG_ENV_ADDR \
438 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
439 #define CONFIG_ENV_SECT_SIZE 0x20000
440 #define CONFIG_ENV_SIZE 0x2000
441
442
443#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
444#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
445
446#else
447 #define CONFIG_ENV_IS_NOWHERE 1
448 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
449 #define CONFIG_ENV_SIZE 0x2000
450#endif
451
452#define CONFIG_LOADS_ECHO 1
453#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
454
455
456
457
458#define CONFIG_BOOTP_BOOTFILESIZE
459#define CONFIG_BOOTP_BOOTPATH
460#define CONFIG_BOOTP_GATEWAY
461#define CONFIG_BOOTP_HOSTNAME
462
463
464
465
466
467#if defined(CONFIG_PCI)
468 #define CONFIG_CMD_PCI
469#endif
470
471#undef CONFIG_WATCHDOG
472
473
474
475
476#define CONFIG_SYS_LONGHELP
477#define CONFIG_SYS_LOAD_ADDR 0x2000000
478
479#if defined(CONFIG_CMD_KGDB)
480 #define CONFIG_SYS_CBSIZE 1024
481#else
482 #define CONFIG_SYS_CBSIZE 256
483#endif
484
485
486#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
487#define CONFIG_SYS_MAXARGS 16
488
489#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
490
491
492
493
494
495
496
497#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
498#define CONFIG_SYS_BOOTM_LEN (64 << 20)
499
500#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
501
502#if 1
503#define CONFIG_SYS_HRCW_LOW (\
504 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
505 HRCWL_DDR_TO_SCB_CLK_1X1 |\
506 HRCWL_CSB_TO_CLKIN |\
507 HRCWL_VCO_1X2 |\
508 HRCWL_CORE_TO_CSB_2X1)
509#elif 0
510#define CONFIG_SYS_HRCW_LOW (\
511 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
512 HRCWL_DDR_TO_SCB_CLK_1X1 |\
513 HRCWL_CSB_TO_CLKIN |\
514 HRCWL_VCO_1X4 |\
515 HRCWL_CORE_TO_CSB_3X1)
516#elif 0
517#define CONFIG_SYS_HRCW_LOW (\
518 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
519 HRCWL_DDR_TO_SCB_CLK_1X1 |\
520 HRCWL_CSB_TO_CLKIN |\
521 HRCWL_VCO_1X4 |\
522 HRCWL_CORE_TO_CSB_2X1)
523#elif 0
524#define CONFIG_SYS_HRCW_LOW (\
525 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
526 HRCWL_DDR_TO_SCB_CLK_1X1 |\
527 HRCWL_CSB_TO_CLKIN |\
528 HRCWL_VCO_1X4 |\
529 HRCWL_CORE_TO_CSB_1X1)
530#elif 0
531#define CONFIG_SYS_HRCW_LOW (\
532 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
533 HRCWL_DDR_TO_SCB_CLK_1X1 |\
534 HRCWL_CSB_TO_CLKIN |\
535 HRCWL_VCO_1X4 |\
536 HRCWL_CORE_TO_CSB_1X1)
537#endif
538
539#ifdef CONFIG_PCISLAVE
540#define CONFIG_SYS_HRCW_HIGH (\
541 HRCWH_PCI_AGENT |\
542 HRCWH_64_BIT_PCI |\
543 HRCWH_PCI1_ARBITER_DISABLE |\
544 HRCWH_PCI2_ARBITER_DISABLE |\
545 HRCWH_CORE_ENABLE |\
546 HRCWH_FROM_0X00000100 |\
547 HRCWH_BOOTSEQ_DISABLE |\
548 HRCWH_SW_WATCHDOG_DISABLE |\
549 HRCWH_ROM_LOC_LOCAL_16BIT |\
550 HRCWH_TSEC1M_IN_GMII |\
551 HRCWH_TSEC2M_IN_GMII)
552#else
553#if defined(PCI_64BIT)
554#define CONFIG_SYS_HRCW_HIGH (\
555 HRCWH_PCI_HOST |\
556 HRCWH_64_BIT_PCI |\
557 HRCWH_PCI1_ARBITER_ENABLE |\
558 HRCWH_PCI2_ARBITER_DISABLE |\
559 HRCWH_CORE_ENABLE |\
560 HRCWH_FROM_0X00000100 |\
561 HRCWH_BOOTSEQ_DISABLE |\
562 HRCWH_SW_WATCHDOG_DISABLE |\
563 HRCWH_ROM_LOC_LOCAL_16BIT |\
564 HRCWH_TSEC1M_IN_GMII |\
565 HRCWH_TSEC2M_IN_GMII)
566#else
567#define CONFIG_SYS_HRCW_HIGH (\
568 HRCWH_PCI_HOST |\
569 HRCWH_32_BIT_PCI |\
570 HRCWH_PCI1_ARBITER_ENABLE |\
571 HRCWH_PCI2_ARBITER_ENABLE |\
572 HRCWH_CORE_ENABLE |\
573 HRCWH_FROM_0X00000100 |\
574 HRCWH_BOOTSEQ_DISABLE |\
575 HRCWH_SW_WATCHDOG_DISABLE |\
576 HRCWH_ROM_LOC_LOCAL_16BIT |\
577 HRCWH_TSEC1M_IN_GMII |\
578 HRCWH_TSEC2M_IN_GMII)
579#endif
580#endif
581
582
583
584
585#define CONFIG_SYS_ACR_PIPE_DEP 3
586#define CONFIG_SYS_ACR_RPTCNT 3
587#define CONFIG_SYS_SPCR_TSEC1EP 3
588#define CONFIG_SYS_SPCR_TSEC2EP 3
589#define CONFIG_SYS_SCCR_TSEC1CM 1
590#define CONFIG_SYS_SCCR_TSEC2CM 1
591
592
593#define CONFIG_SYS_SICRH 0
594#define CONFIG_SYS_SICRL SICRL_LDP_A
595
596#define CONFIG_SYS_HID0_INIT 0x000000000
597#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
598 | HID0_ENABLE_INSTRUCTION_CACHE)
599
600
601
602
603
604
605#define CONFIG_SYS_HID2 HID2_HBE
606#define CONFIG_HIGH_BATS 1
607
608
609#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
610 | BATL_PP_RW \
611 | BATL_MEMCOHERENCE)
612#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
613 | BATU_BL_256M \
614 | BATU_VS \
615 | BATU_VP)
616
617
618#ifdef CONFIG_PCI
619#define CONFIG_PCI_INDIRECT_BRIDGE
620#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
621 | BATL_PP_RW \
622 | BATL_MEMCOHERENCE)
623#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
624 | BATU_BL_256M \
625 | BATU_VS \
626 | BATU_VP)
627#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
628 | BATL_PP_RW \
629 | BATL_CACHEINHIBIT \
630 | BATL_GUARDEDSTORAGE)
631#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
632 | BATU_BL_256M \
633 | BATU_VS \
634 | BATU_VP)
635#else
636#define CONFIG_SYS_IBAT1L (0)
637#define CONFIG_SYS_IBAT1U (0)
638#define CONFIG_SYS_IBAT2L (0)
639#define CONFIG_SYS_IBAT2U (0)
640#endif
641
642#ifdef CONFIG_MPC83XX_PCI2
643#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
644 | BATL_PP_RW \
645 | BATL_MEMCOHERENCE)
646#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
647 | BATU_BL_256M \
648 | BATU_VS \
649 | BATU_VP)
650#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
651 | BATL_PP_RW \
652 | BATL_CACHEINHIBIT \
653 | BATL_GUARDEDSTORAGE)
654#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
655 | BATU_BL_256M \
656 | BATU_VS \
657 | BATU_VP)
658#else
659#define CONFIG_SYS_IBAT3L (0)
660#define CONFIG_SYS_IBAT3U (0)
661#define CONFIG_SYS_IBAT4L (0)
662#define CONFIG_SYS_IBAT4U (0)
663#endif
664
665
666#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
667 | BATL_PP_RW \
668 | BATL_CACHEINHIBIT \
669 | BATL_GUARDEDSTORAGE)
670#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
671 | BATU_BL_256M \
672 | BATU_VS \
673 | BATU_VP)
674
675
676#define CONFIG_SYS_IBAT6L (0xF0000000 \
677 | BATL_PP_RW \
678 | BATL_MEMCOHERENCE \
679 | BATL_GUARDEDSTORAGE)
680#define CONFIG_SYS_IBAT6U (0xF0000000 \
681 | BATU_BL_256M \
682 | BATU_VS \
683 | BATU_VP)
684
685#define CONFIG_SYS_IBAT7L (0)
686#define CONFIG_SYS_IBAT7U (0)
687
688#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
689#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
690#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
691#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
692#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
693#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
694#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
695#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
696#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
697#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
698#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
699#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
700#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
701#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
702#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
703#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
704
705#if defined(CONFIG_CMD_KGDB)
706#define CONFIG_KGDB_BAUDRATE 230400
707#endif
708
709
710
711
712#define CONFIG_ENV_OVERWRITE
713
714#if defined(CONFIG_TSEC_ENET)
715#define CONFIG_HAS_ETH1
716#define CONFIG_HAS_ETH0
717#endif
718
719#define CONFIG_HOSTNAME mpc8349emds
720#define CONFIG_ROOTPATH "/nfsroot/rootfs"
721#define CONFIG_BOOTFILE "uImage"
722
723#define CONFIG_LOADADDR 800000
724
725#undef CONFIG_BOOTARGS
726
727#define CONFIG_PREBOOT "echo;" \
728 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
729 "echo"
730
731#define CONFIG_EXTRA_ENV_SETTINGS \
732 "netdev=eth0\0" \
733 "hostname=mpc8349emds\0" \
734 "nfsargs=setenv bootargs root=/dev/nfs rw " \
735 "nfsroot=${serverip}:${rootpath}\0" \
736 "ramargs=setenv bootargs root=/dev/ram rw\0" \
737 "addip=setenv bootargs ${bootargs} " \
738 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
739 ":${hostname}:${netdev}:off panic=1\0" \
740 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
741 "flash_nfs=run nfsargs addip addtty;" \
742 "bootm ${kernel_addr}\0" \
743 "flash_self=run ramargs addip addtty;" \
744 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
745 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
746 "bootm\0" \
747 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
748 "update=protect off fe000000 fe03ffff; " \
749 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
750 "upd=run load update\0" \
751 "fdtaddr=780000\0" \
752 "fdtfile=mpc834x_mds.dtb\0" \
753 ""
754
755#define CONFIG_NFSBOOTCOMMAND \
756 "setenv bootargs root=/dev/nfs rw " \
757 "nfsroot=$serverip:$rootpath " \
758 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
759 "$netdev:off " \
760 "console=$consoledev,$baudrate $othbootargs;" \
761 "tftp $loadaddr $bootfile;" \
762 "tftp $fdtaddr $fdtfile;" \
763 "bootm $loadaddr - $fdtaddr"
764
765#define CONFIG_RAMBOOTCOMMAND \
766 "setenv bootargs root=/dev/ram rw " \
767 "console=$consoledev,$baudrate $othbootargs;" \
768 "tftp $ramdiskaddr $ramdiskfile;" \
769 "tftp $loadaddr $bootfile;" \
770 "tftp $fdtaddr $fdtfile;" \
771 "bootm $loadaddr $ramdiskaddr $fdtaddr"
772
773#define CONFIG_BOOTCOMMAND "run flash_self"
774
775#endif
776