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39
40#ifndef __CONFIG_H
41#define __CONFIG_H
42
43#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
44#define CONFIG_SYS_LOWBOOT
45#endif
46
47
48
49
50#define CONFIG_MPC834x
51#define CONFIG_MPC8349
52
53#ifndef CONFIG_SYS_TEXT_BASE
54#define CONFIG_SYS_TEXT_BASE 0xFEF00000
55#endif
56
57#define CONFIG_SYS_IMMR 0xE0000000
58
59#define CONFIG_MISC_INIT_F
60#define CONFIG_MISC_INIT_R
61
62
63
64
65
66#ifdef CONFIG_MPC8349ITX
67
68#define CONFIG_COMPACT_FLASH
69#define CONFIG_VSC7385_ENET
70#define CONFIG_SATA_SIL3114
71#define CONFIG_SYS_USB_HOST
72#endif
73
74#define CONFIG_RTC_DS1337
75#define CONFIG_SYS_I2C
76#define CONFIG_TSEC_ENET
77
78
79
80
81
82
83#ifdef CONFIG_SYS_I2C
84#define CONFIG_SYS_I2C_FSL
85#define CONFIG_SYS_FSL_I2C_SPEED 400000
86#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
87#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
88#define CONFIG_SYS_FSL_I2C2_SPEED 400000
89#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
90#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
91
92#define CONFIG_SYS_SPD_BUS_NUM 1
93#define CONFIG_SYS_RTC_BUS_NUM 1
94
95#define CONFIG_SYS_I2C_8574_ADDR1 0x20
96#define CONFIG_SYS_I2C_8574_ADDR2 0x21
97#define CONFIG_SYS_I2C_8574A_ADDR1 0x38
98#define CONFIG_SYS_I2C_8574A_ADDR2 0x39
99#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
100#define CONFIG_SYS_I2C_RTC_ADDR 0x68
101#define SPD_EEPROM_ADDRESS 0x51
102
103
104#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
105 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
106 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
107 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
108
109
110#define I2C_8574_REVISION 0x03
111#define I2C_8574_CF 0x08
112#define I2C_8574_MPCICLKRN 0x10
113#define I2C_8574_PCI66 0x20
114#define I2C_8574_FLASHSIDE 0x40
115
116#endif
117
118
119#ifdef CONFIG_COMPACT_FLASH
120
121#define CONFIG_SYS_IDE_MAXBUS 1
122#define CONFIG_SYS_IDE_MAXDEVICE 1
123
124#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
125#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
126#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
127#define CONFIG_SYS_ATA_REG_OFFSET 0
128#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
129#define CONFIG_SYS_ATA_STRIDE 2
130
131
132#define ATA_RESET_TIME 1
133
134#endif
135
136
137
138
139#ifdef CONFIG_SATA_SIL3114
140
141#define CONFIG_SYS_SATA_MAX_DEVICE 4
142#define CONFIG_LIBATA
143#define CONFIG_LBA48
144
145#endif
146
147#ifdef CONFIG_SYS_USB_HOST
148
149
150
151#define CONFIG_USB_EHCI_FSL
152
153
154
155#if 1
156#define CONFIG_HAS_FSL_MPH_USB
157#else
158#define CONFIG_HAS_FSL_DR_USB
159#endif
160
161#endif
162
163
164
165
166#define CONFIG_SYS_DDR_BASE 0x00000000
167#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
168#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
169#define CONFIG_SYS_83XX_DDR_USES_CS0
170#define CONFIG_SYS_MEMTEST_START 0x1000
171#define CONFIG_SYS_MEMTEST_END 0x2000
172
173#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
174 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
175
176#define CONFIG_VERY_BIG_RAM
177#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
178
179#ifdef CONFIG_SYS_I2C
180#define CONFIG_SPD_EEPROM
181#endif
182
183
184#ifndef CONFIG_SPD_EEPROM
185 #define CONFIG_SYS_DDR_SIZE 256
186 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
187 | CSCONFIG_ROW_BIT_13 \
188 | CSCONFIG_COL_BIT_10)
189
190 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
191 #define CONFIG_SYS_DDR_TIMING_2 0x00000800
192#endif
193
194
195
196
197
198#define CONFIG_SYS_FLASH_CFI
199#define CONFIG_FLASH_CFI_DRIVER
200#define CONFIG_SYS_FLASH_BASE 0xFE000000
201#define CONFIG_SYS_FLASH_EMPTY_INFO
202
203#define CONFIG_SYS_MAX_FLASH_SECT 135
204#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
205#define CONFIG_SYS_FLASH_WRITE_TOUT 500
206#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
207
208
209
210#define CONFIG_SYS_FLASH_QUIET_TEST
211#define CONFIG_SYS_MAX_FLASH_BANKS 2
212#define CONFIG_SYS_FLASH_BANKS_LIST \
213 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
214#define CONFIG_SYS_FLASH_SIZE 16
215#define CONFIG_SYS_FLASH_PROTECTION 1
216
217
218
219#ifdef CONFIG_VSC7385_ENET
220
221#define CONFIG_TSEC2
222
223
224#define CONFIG_VSC7385_IMAGE 0xFEFFE000
225#define CONFIG_VSC7385_IMAGE_SIZE 8192
226
227#endif
228
229
230
231
232
233
234
235#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
236 | BR_PS_16 \
237 | BR_MS_GPCM \
238 | BR_V)
239#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
240 | OR_UPM_XAM \
241 | OR_GPCM_CSNT \
242 | OR_GPCM_ACS_DIV2 \
243 | OR_GPCM_XACS \
244 | OR_GPCM_SCY_15 \
245 | OR_GPCM_TRLX_SET \
246 | OR_GPCM_EHTR_SET \
247 | OR_GPCM_EAD)
248#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
249#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
250
251
252
253#define CONFIG_SYS_VSC7385_BASE 0xF8000000
254
255#ifdef CONFIG_VSC7385_ENET
256
257#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
258 | BR_PS_8 \
259 | BR_MS_GPCM \
260 | BR_V)
261#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
262 | OR_GPCM_CSNT \
263 | OR_GPCM_XACS \
264 | OR_GPCM_SCY_15 \
265 | OR_GPCM_SETA \
266 | OR_GPCM_TRLX_SET \
267 | OR_GPCM_EHTR_SET \
268 | OR_GPCM_EAD)
269
270#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
271#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
272
273#endif
274
275
276
277#define CONFIG_SYS_LED_BASE 0xF9000000
278#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
279 | BR_PS_8 \
280 | BR_MS_GPCM \
281 | BR_V)
282#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
283 | OR_GPCM_CSNT \
284 | OR_GPCM_ACS_DIV2 \
285 | OR_GPCM_XACS \
286 | OR_GPCM_SCY_9 \
287 | OR_GPCM_TRLX_SET \
288 | OR_GPCM_EHTR_SET \
289 | OR_GPCM_EAD)
290
291
292
293#ifdef CONFIG_COMPACT_FLASH
294
295#define CONFIG_SYS_CF_BASE 0xF0000000
296
297#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
298 | BR_PS_16 \
299 | BR_MS_UPMA \
300 | BR_V)
301#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
302
303#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
304#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
305
306#endif
307
308
309
310
311#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
312
313#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
314#define CONFIG_SYS_RAMBOOT
315#else
316#undef CONFIG_SYS_RAMBOOT
317#endif
318
319#define CONFIG_SYS_INIT_RAM_LOCK
320#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
321#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
322
323#define CONFIG_SYS_GBL_DATA_OFFSET \
324 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
325#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
326
327
328#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
329#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
330
331
332
333
334
335
336
337#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
338#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
339#define CONFIG_SYS_LBC_LBCR 0x00000000
340
341
342#define CONFIG_SYS_LBC_LSRT 0x32000000
343
344#define CONFIG_SYS_LBC_MRTPR 0x20000000
345
346
347
348
349#define CONFIG_CONS_INDEX 1
350#define CONFIG_SYS_NS16550_SERIAL
351#define CONFIG_SYS_NS16550_REG_SIZE 1
352#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
353
354#define CONFIG_SYS_BAUDRATE_TABLE \
355 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
356
357#define CONSOLE ttyS0
358
359#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
360#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
361
362
363
364
365#ifdef CONFIG_PCI
366#define CONFIG_PCI_INDIRECT_BRIDGE
367
368#define CONFIG_MPC83XX_PCI2
369
370
371
372
373
374#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
375#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
376#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
377#define CONFIG_SYS_PCI1_MMIO_BASE \
378 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
379#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
380#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
381#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
382#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
383#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
384
385#ifdef CONFIG_MPC83XX_PCI2
386#define CONFIG_SYS_PCI2_MEM_BASE \
387 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
388#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
389#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
390#define CONFIG_SYS_PCI2_MMIO_BASE \
391 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
392#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
393#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
394#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
395#define CONFIG_SYS_PCI2_IO_PHYS \
396 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
397#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000
398#endif
399
400#ifndef CONFIG_PCI_PNP
401 #define PCI_ENET0_IOADDR 0x00000000
402 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
403 #define PCI_IDSEL_NUMBER 0x0f
404#endif
405
406#define CONFIG_PCI_SCAN_SHOW
407
408#endif
409
410#define CONFIG_PCI_66M
411#ifdef CONFIG_PCI_66M
412#define CONFIG_83XX_CLKIN 66666666
413#else
414#define CONFIG_83XX_CLKIN 33333333
415#endif
416
417
418
419#ifdef CONFIG_TSEC_ENET
420
421#define CONFIG_MII
422#define CONFIG_PHY_GIGE
423
424#define CONFIG_TSEC1
425
426#ifdef CONFIG_TSEC1
427#define CONFIG_HAS_ETH0
428#define CONFIG_TSEC1_NAME "TSEC0"
429#define CONFIG_SYS_TSEC1_OFFSET 0x24000
430#define TSEC1_PHY_ADDR 0x1c
431#define TSEC1_PHYIDX 0
432#define TSEC1_FLAGS TSEC_GIGABIT
433#endif
434
435#ifdef CONFIG_TSEC2
436#define CONFIG_HAS_ETH1
437#define CONFIG_TSEC2_NAME "TSEC1"
438#define CONFIG_SYS_TSEC2_OFFSET 0x25000
439
440#define TSEC2_PHY_ADDR 4
441#define TSEC2_PHYIDX 0
442#define TSEC2_FLAGS TSEC_GIGABIT
443#endif
444
445#define CONFIG_ETHPRIME "Freescale TSEC"
446
447#endif
448
449
450
451
452#define CONFIG_ENV_OVERWRITE
453
454#ifndef CONFIG_SYS_RAMBOOT
455 #define CONFIG_ENV_IS_IN_FLASH
456 #define CONFIG_ENV_ADDR \
457 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
458 #define CONFIG_ENV_SECT_SIZE 0x10000
459 #define CONFIG_ENV_SIZE 0x2000
460#else
461 #undef CONFIG_FLASH_CFI_DRIVER
462 #define CONFIG_ENV_IS_NOWHERE
463 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
464 #define CONFIG_ENV_SIZE 0x2000
465#endif
466
467#define CONFIG_LOADS_ECHO
468#define CONFIG_SYS_LOADS_BAUD_CHANGE
469
470
471
472
473#define CONFIG_BOOTP_BOOTFILESIZE
474#define CONFIG_BOOTP_BOOTPATH
475#define CONFIG_BOOTP_GATEWAY
476#define CONFIG_BOOTP_HOSTNAME
477
478
479
480
481#define CONFIG_CMD_SDRAM
482
483#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
484 || defined(CONFIG_USB_STORAGE)
485 #define CONFIG_SUPPORT_VFAT
486#endif
487
488#ifdef CONFIG_SATA_SIL3114
489 #define CONFIG_CMD_SATA
490#endif
491
492#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
493#endif
494
495#ifdef CONFIG_PCI
496 #define CONFIG_CMD_PCI
497#endif
498
499
500#undef CONFIG_WATCHDOG
501
502
503
504
505#define CONFIG_SYS_LONGHELP
506#define CONFIG_CMDLINE_EDITING
507#define CONFIG_AUTO_COMPLETE
508
509#define CONFIG_SYS_LOAD_ADDR 0x2000000
510#define CONFIG_LOADADDR 800000
511
512#if defined(CONFIG_CMD_KGDB)
513 #define CONFIG_SYS_CBSIZE 1024
514#else
515 #define CONFIG_SYS_CBSIZE 256
516#endif
517
518
519#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
520#define CONFIG_SYS_MAXARGS 16
521
522#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
523
524
525
526
527
528
529
530#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
531#define CONFIG_SYS_BOOTM_LEN (64 << 20)
532
533#define CONFIG_SYS_HRCW_LOW (\
534 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
535 HRCWL_DDR_TO_SCB_CLK_1X1 |\
536 HRCWL_CSB_TO_CLKIN_4X1 |\
537 HRCWL_VCO_1X2 |\
538 HRCWL_CORE_TO_CSB_2X1)
539
540#ifdef CONFIG_SYS_LOWBOOT
541#define CONFIG_SYS_HRCW_HIGH (\
542 HRCWH_PCI_HOST |\
543 HRCWH_32_BIT_PCI |\
544 HRCWH_PCI1_ARBITER_ENABLE |\
545 HRCWH_PCI2_ARBITER_ENABLE |\
546 HRCWH_CORE_ENABLE |\
547 HRCWH_FROM_0X00000100 |\
548 HRCWH_BOOTSEQ_DISABLE |\
549 HRCWH_SW_WATCHDOG_DISABLE |\
550 HRCWH_ROM_LOC_LOCAL_16BIT |\
551 HRCWH_TSEC1M_IN_GMII |\
552 HRCWH_TSEC2M_IN_GMII)
553#else
554#define CONFIG_SYS_HRCW_HIGH (\
555 HRCWH_PCI_HOST |\
556 HRCWH_32_BIT_PCI |\
557 HRCWH_PCI1_ARBITER_ENABLE |\
558 HRCWH_PCI2_ARBITER_ENABLE |\
559 HRCWH_CORE_ENABLE |\
560 HRCWH_FROM_0XFFF00100 |\
561 HRCWH_BOOTSEQ_DISABLE |\
562 HRCWH_SW_WATCHDOG_DISABLE |\
563 HRCWH_ROM_LOC_LOCAL_16BIT |\
564 HRCWH_TSEC1M_IN_GMII |\
565 HRCWH_TSEC2M_IN_GMII)
566#endif
567
568
569
570
571#define CONFIG_SYS_ACR_PIPE_DEP 3
572#define CONFIG_SYS_ACR_RPTCNT 3
573#define CONFIG_SYS_SPCR_TSEC1EP 3
574#define CONFIG_SYS_SPCR_TSEC2EP 3
575#define CONFIG_SYS_SCCR_TSEC1CM 1
576#define CONFIG_SYS_SCCR_TSEC2CM 1
577#define CONFIG_SYS_SCCR_USBMPHCM 3
578#define CONFIG_SYS_SCCR_USBDRCM 0
579
580
581
582
583
584#define CONFIG_SYS_SICRH SICRH_TSOBI1
585
586#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
587
588#define CONFIG_SYS_HID0_INIT 0x00000000
589#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
590
591#define CONFIG_SYS_HID2 HID2_HBE
592#define CONFIG_HIGH_BATS 1
593
594
595#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
596 | BATL_PP_RW \
597 | BATL_MEMCOHERENCE)
598#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
599 | BATU_BL_256M \
600 | BATU_VS \
601 | BATU_VP)
602
603
604#ifdef CONFIG_PCI
605#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
606 | BATL_PP_RW \
607 | BATL_MEMCOHERENCE)
608#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
609 | BATU_BL_256M \
610 | BATU_VS \
611 | BATU_VP)
612#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
613 | BATL_PP_RW \
614 | BATL_CACHEINHIBIT \
615 | BATL_GUARDEDSTORAGE)
616#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
617 | BATU_BL_256M \
618 | BATU_VS \
619 | BATU_VP)
620#else
621#define CONFIG_SYS_IBAT1L 0
622#define CONFIG_SYS_IBAT1U 0
623#define CONFIG_SYS_IBAT2L 0
624#define CONFIG_SYS_IBAT2U 0
625#endif
626
627#ifdef CONFIG_MPC83XX_PCI2
628#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
629 | BATL_PP_RW \
630 | BATL_MEMCOHERENCE)
631#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
632 | BATU_BL_256M \
633 | BATU_VS \
634 | BATU_VP)
635#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
636 | BATL_PP_RW \
637 | BATL_CACHEINHIBIT \
638 | BATL_GUARDEDSTORAGE)
639#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
640 | BATU_BL_256M \
641 | BATU_VS \
642 | BATU_VP)
643#else
644#define CONFIG_SYS_IBAT3L 0
645#define CONFIG_SYS_IBAT3U 0
646#define CONFIG_SYS_IBAT4L 0
647#define CONFIG_SYS_IBAT4U 0
648#endif
649
650
651#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
652 | BATL_PP_RW \
653 | BATL_CACHEINHIBIT \
654 | BATL_GUARDEDSTORAGE)
655#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
656 | BATU_BL_256M \
657 | BATU_VS \
658 | BATU_VP)
659
660
661#define CONFIG_SYS_IBAT6L (0xF0000000 \
662 | BATL_PP_RW \
663 | BATL_MEMCOHERENCE \
664 | BATL_GUARDEDSTORAGE)
665#define CONFIG_SYS_IBAT6U (0xF0000000 \
666 | BATU_BL_256M \
667 | BATU_VS \
668 | BATU_VP)
669
670#define CONFIG_SYS_IBAT7L 0
671#define CONFIG_SYS_IBAT7U 0
672
673#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
674#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
675#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
676#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
677#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
678#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
679#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
680#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
681#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
682#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
683#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
684#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
685#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
686#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
687#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
688#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
689
690#if defined(CONFIG_CMD_KGDB)
691#define CONFIG_KGDB_BAUDRATE 230400
692#endif
693
694
695
696
697#define CONFIG_ENV_OVERWRITE
698
699#define CONFIG_NETDEV "eth0"
700
701#ifdef CONFIG_MPC8349ITX
702#define CONFIG_HOSTNAME "mpc8349emitx"
703#else
704#define CONFIG_HOSTNAME "mpc8349emitxgp"
705#endif
706
707
708#define CONFIG_ROOTPATH "/nfsroot/rootfs"
709#define CONFIG_BOOTFILE "uImage"
710
711#define CONFIG_UBOOTPATH "u-boot.bin"
712
713#ifdef CONFIG_MPC8349ITX
714#define CONFIG_FDTFILE "mpc8349emitx.dtb"
715#else
716#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
717#endif
718
719
720#define CONFIG_BOOTARGS \
721 "root=/dev/nfs rw" \
722 " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
723 " ip=" __stringify(CONFIG_IPADDR) ":" \
724 __stringify(CONFIG_SERVERIP) ":" \
725 __stringify(CONFIG_GATEWAYIP) ":" \
726 __stringify(CONFIG_NETMASK) ":" \
727 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
728 " console=" __stringify(CONSOLE) "," __stringify(CONFIG_BAUDRATE)
729
730#define CONFIG_EXTRA_ENV_SETTINGS \
731 "console=" __stringify(CONSOLE) "\0" \
732 "netdev=" CONFIG_NETDEV "\0" \
733 "uboot=" CONFIG_UBOOTPATH "\0" \
734 "tftpflash=tftpboot $loadaddr $uboot; " \
735 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
736 " +$filesize; " \
737 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
738 " +$filesize; " \
739 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
740 " $filesize; " \
741 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
742 " +$filesize; " \
743 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
744 " $filesize\0" \
745 "fdtaddr=780000\0" \
746 "fdtfile=" CONFIG_FDTFILE "\0"
747
748#define CONFIG_NFSBOOTCOMMAND \
749 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
750 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
751 " console=$console,$baudrate $othbootargs; " \
752 "tftp $loadaddr $bootfile;" \
753 "tftp $fdtaddr $fdtfile;" \
754 "bootm $loadaddr - $fdtaddr"
755
756#define CONFIG_RAMBOOTCOMMAND \
757 "setenv bootargs root=/dev/ram rw" \
758 " console=$console,$baudrate $othbootargs; " \
759 "tftp $ramdiskaddr $ramdiskfile;" \
760 "tftp $loadaddr $bootfile;" \
761 "tftp $fdtaddr $fdtfile;" \
762 "bootm $loadaddr $ramdiskaddr $fdtaddr"
763
764#endif
765