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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#include "../board/freescale/common/ics307_clk.h"
15
16#ifdef CONFIG_SDCARD
17#define CONFIG_RAMBOOT_SDCARD 1
18#define CONFIG_SYS_TEXT_BASE 0xf8f40000
19#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
20#endif
21
22#ifdef CONFIG_SPIFLASH
23#define CONFIG_RAMBOOT_SPIFLASH 1
24#define CONFIG_SYS_TEXT_BASE 0xf8f40000
25#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
26#endif
27
28#ifndef CONFIG_SYS_TEXT_BASE
29#define CONFIG_SYS_TEXT_BASE 0xeff40000
30#endif
31
32#ifndef CONFIG_RESET_VECTOR_ADDRESS
33#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
34#endif
35
36#ifndef CONFIG_SYS_MONITOR_BASE
37#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
38#endif
39
40#define CONFIG_PCI1 1
41#define CONFIG_PCIE1 1
42#define CONFIG_PCIE2 1
43#define CONFIG_PCIE3 1
44#define CONFIG_FSL_PCI_INIT 1
45#define CONFIG_PCI_INDIRECT_BRIDGE 1
46#define CONFIG_FSL_PCIE_RESET 1
47#define CONFIG_SYS_PCI_64BIT 1
48
49
50#define CONFIG_TSEC_ENET
51#define CONFIG_ENV_OVERWRITE
52
53#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
54#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
55#define CONFIG_ICS307_REFCLK_HZ 33333000
56
57
58
59
60#define CONFIG_L2_CACHE
61#define CONFIG_BTB
62
63#define CONFIG_ENABLE_36BIT_PHYS 1
64
65#ifdef CONFIG_PHYS_64BIT
66#define CONFIG_ADDR_MAP 1
67#define CONFIG_SYS_NUM_ADDR_MAP 16
68#endif
69
70#define CONFIG_SYS_MEMTEST_START 0x00010000
71#define CONFIG_SYS_MEMTEST_END 0x1f000000
72#define CONFIG_PANIC_HANG
73
74
75
76
77#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
78#ifdef CONFIG_PHYS_64BIT
79#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
80#else
81#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
82#endif
83#define CONFIG_SYS_L2_SIZE (512 << 10)
84#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
85
86#define CONFIG_SYS_CCSRBAR 0xffe00000
87#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
88
89#if defined(CONFIG_NAND_SPL)
90#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
91#endif
92
93
94#define CONFIG_VERY_BIG_RAM
95#undef CONFIG_FSL_DDR_INTERACTIVE
96#define CONFIG_SPD_EEPROM
97#define CONFIG_DDR_SPD
98
99#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
100#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
101
102#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
103#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
104
105#define CONFIG_DIMM_SLOTS_PER_CTLR 1
106#define CONFIG_CHIP_SELECTS_PER_CTRL 2
107
108
109#define SPD_EEPROM_ADDRESS 0x51
110#define CONFIG_SYS_SPD_BUS_NUM 1
111
112
113#define CONFIG_SYS_SDRAM_SIZE 256
114#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
115#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
116#define CONFIG_SYS_DDR_TIMING_3 0x00000000
117#define CONFIG_SYS_DDR_TIMING_0 0x00260802
118#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
119#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
120#define CONFIG_SYS_DDR_MODE_1 0x00480432
121#define CONFIG_SYS_DDR_MODE_2 0x00000000
122#define CONFIG_SYS_DDR_INTERVAL 0x06180100
123#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
124#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
125#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
126#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
127#define CONFIG_SYS_DDR_CONTROL 0xC3008000
128#define CONFIG_SYS_DDR_CONTROL2 0x04400010
129
130#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
131#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
132#define CONFIG_SYS_DDR_SBE 0x00010000
133
134
135#ifndef CONFIG_SPD_EEPROM
136#error ("CONFIG_SPD_EEPROM is required")
137#endif
138
139#undef CONFIG_CLOCKS_IN_MHZ
140
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161
162
163
164#define CONFIG_SYS_FLASH_BASE 0xe0000000
165#ifdef CONFIG_PHYS_64BIT
166#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
167#else
168#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
169#endif
170
171#define CONFIG_FLASH_BR_PRELIM \
172 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
173#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
174
175#define CONFIG_SYS_BR1_PRELIM \
176 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
177 | BR_PS_16 | BR_V)
178#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
179
180#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
181 CONFIG_SYS_FLASH_BASE_PHYS }
182#define CONFIG_SYS_FLASH_QUIET_TEST
183#define CONFIG_FLASH_SHOW_PROGRESS 45
184
185#define CONFIG_SYS_MAX_FLASH_BANKS 2
186#define CONFIG_SYS_MAX_FLASH_SECT 1024
187#undef CONFIG_SYS_FLASH_CHECKSUM
188#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
189#define CONFIG_SYS_FLASH_WRITE_TOUT 500
190
191#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
192#define CONFIG_SYS_RAMBOOT
193#define CONFIG_SYS_EXTRA_ENV_RELOC
194#else
195#undef CONFIG_SYS_RAMBOOT
196#endif
197
198#define CONFIG_FLASH_CFI_DRIVER
199#define CONFIG_SYS_FLASH_CFI
200#define CONFIG_SYS_FLASH_EMPTY_INFO
201#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
202
203#define CONFIG_BOARD_EARLY_INIT_R
204
205#define CONFIG_HWCONFIG
206#define CONFIG_FSL_PIXIS 1
207#define PIXIS_BASE 0xffdf0000
208#ifdef CONFIG_PHYS_64BIT
209#define PIXIS_BASE_PHYS 0xfffdf0000ull
210#else
211#define PIXIS_BASE_PHYS PIXIS_BASE
212#endif
213
214#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
215#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
216
217#define PIXIS_ID 0x0
218#define PIXIS_VER 0x1
219#define PIXIS_PVER 0x2
220#define PIXIS_CSR 0x3
221#define PIXIS_RST 0x4
222#define PIXIS_PWR 0x5
223#define PIXIS_AUX 0x6
224#define PIXIS_SPD 0x7
225#define PIXIS_AUX2 0x8
226#define PIXIS_VCTL 0x10
227#define PIXIS_VSTAT 0x11
228#define PIXIS_VCFGEN0 0x12
229#define PIXIS_VCFGEN1 0x13
230#define PIXIS_VCORE0 0x14
231#define PIXIS_VBOOT 0x16
232#define PIXIS_VBOOT_LBMAP 0xe0
233#define PIXIS_VBOOT_LBMAP_NOR0 0x00
234#define PIXIS_VBOOT_LBMAP_NOR1 0x01
235#define PIXIS_VBOOT_LBMAP_NOR2 0x02
236#define PIXIS_VBOOT_LBMAP_NOR3 0x03
237#define PIXIS_VBOOT_LBMAP_PJET 0x04
238#define PIXIS_VBOOT_LBMAP_NAND 0x05
239#define PIXIS_VSPEED0 0x17
240#define PIXIS_VSPEED1 0x18
241#define PIXIS_VSPEED2 0x19
242#define PIXIS_VSYSCLK0 0x1A
243#define PIXIS_VSYSCLK1 0x1B
244#define PIXIS_VSYSCLK2 0x1C
245#define PIXIS_VDDRCLK0 0x1D
246#define PIXIS_VDDRCLK1 0x1E
247#define PIXIS_VDDRCLK2 0x1F
248#define PIXIS_VWATCH 0x24
249#define PIXIS_LED 0x25
250
251#define PIXIS_SPD_SYSCLK 0x7
252
253
254#define PIXIS_VCLKH 0x19
255#define PIXIS_VCLKL 0x1A
256#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
257
258#define CONFIG_SYS_INIT_RAM_LOCK 1
259#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
260#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
261
262#define CONFIG_SYS_GBL_DATA_OFFSET \
263 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
264#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
265
266#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
267#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
268
269#ifndef CONFIG_NAND_SPL
270#define CONFIG_SYS_NAND_BASE 0xffa00000
271#ifdef CONFIG_PHYS_64BIT
272#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
273#else
274#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
275#endif
276#else
277#define CONFIG_SYS_NAND_BASE 0xfff00000
278#ifdef CONFIG_PHYS_64BIT
279#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
280#else
281#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
282#endif
283#endif
284#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
285 CONFIG_SYS_NAND_BASE + 0x40000, \
286 CONFIG_SYS_NAND_BASE + 0x80000, \
287 CONFIG_SYS_NAND_BASE + 0xC0000}
288#define CONFIG_SYS_MAX_NAND_DEVICE 4
289#define CONFIG_CMD_NAND 1
290#define CONFIG_NAND_FSL_ELBC 1
291#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
292
293
294#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
295#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
296#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
297#define CONFIG_SYS_NAND_U_BOOT_START \
298 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
299#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
300#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
301#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
302
303
304#define CONFIG_SYS_NAND_BR_PRELIM \
305 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
306 | (2<<BR_DECC_SHIFT) \
307 | BR_PS_8 \
308 | BR_MS_FCM \
309 | BR_V)
310#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
311 | OR_FCM_PGS \
312 | OR_FCM_CSCT \
313 | OR_FCM_CST \
314 | OR_FCM_CHT \
315 | OR_FCM_SCY_1 \
316 | OR_FCM_TRLX \
317 | OR_FCM_EHTR)
318
319#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
320#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
321#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM
322#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM
323
324#define CONFIG_SYS_BR4_PRELIM \
325 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
326 | (2<<BR_DECC_SHIFT) \
327 | BR_PS_8 \
328 | BR_MS_FCM \
329 | BR_V)
330#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM
331#define CONFIG_SYS_BR5_PRELIM \
332 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
333 | (2<<BR_DECC_SHIFT) \
334 | BR_PS_8 \
335 | BR_MS_FCM \
336 | BR_V)
337#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM
338
339#define CONFIG_SYS_BR6_PRELIM \
340 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
341 | (2<<BR_DECC_SHIFT) \
342 | BR_PS_8 \
343 | BR_MS_FCM \
344 | BR_V)
345#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM
346
347
348
349
350
351#define CONFIG_CONS_INDEX 1
352#define CONFIG_SYS_NS16550_SERIAL
353#define CONFIG_SYS_NS16550_REG_SIZE 1
354#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
355#ifdef CONFIG_NAND_SPL
356#define CONFIG_NS16550_MIN_FUNCTIONS
357#endif
358
359#define CONFIG_SYS_BAUDRATE_TABLE \
360 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
361
362#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
363#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
364
365
366
367
368#define CONFIG_SYS_I2C
369#define CONFIG_SYS_I2C_FSL
370#define CONFIG_SYS_FSL_I2C_SPEED 400000
371#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
372#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
373#define CONFIG_SYS_FSL_I2C2_SPEED 400000
374#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
375#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
376#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
377
378
379
380
381#define CONFIG_ID_EEPROM
382#ifdef CONFIG_ID_EEPROM
383#define CONFIG_SYS_I2C_EEPROM_NXID
384#endif
385#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
386#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
387#define CONFIG_SYS_EEPROM_BUS_NUM 1
388
389
390
391
392#define CONFIG_HARD_SPI
393
394#if defined(CONFIG_SPI_FLASH)
395#define CONFIG_SF_DEFAULT_SPEED 10000000
396#define CONFIG_SF_DEFAULT_MODE 0
397#endif
398
399
400
401
402
403
404#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
405#ifdef CONFIG_PHYS_64BIT
406#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
407#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
408#else
409#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
410#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
411#endif
412#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
413#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
414#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
415#ifdef CONFIG_PHYS_64BIT
416#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
417#else
418#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
419#endif
420#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000
421
422
423#define CONFIG_SYS_PCIE1_NAME "Slot 1"
424#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
425#ifdef CONFIG_PHYS_64BIT
426#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
427#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
428#else
429#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
430#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
431#endif
432#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000
433#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
434#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
435#ifdef CONFIG_PHYS_64BIT
436#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
437#else
438#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
439#endif
440#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
441
442
443#define CONFIG_SYS_PCIE2_NAME "Slot 2"
444#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
445#ifdef CONFIG_PHYS_64BIT
446#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
447#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
448#else
449#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
450#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
451#endif
452#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000
453#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
454#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
455#ifdef CONFIG_PHYS_64BIT
456#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
457#else
458#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
459#endif
460#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
461
462
463#define CONFIG_SYS_PCIE3_NAME "Slot 3"
464#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
465#ifdef CONFIG_PHYS_64BIT
466#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
467#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
468#else
469#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
470#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
471#endif
472#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
473#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
474#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
475#ifdef CONFIG_PHYS_64BIT
476#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
477#else
478#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
479#endif
480#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
481
482#if defined(CONFIG_PCI)
483
484#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
485
486
487
488
489
490
491#if defined(CONFIG_VIDEO)
492#define CONFIG_BIOSEMU
493#define CONFIG_ATI_RADEON_FB
494#define CONFIG_VIDEO_LOGO
495#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
496#endif
497
498#undef CONFIG_EEPRO100
499#undef CONFIG_TULIP
500
501#ifndef CONFIG_PCI_PNP
502 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
503 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
504 #define PCI_IDSEL_NUMBER 0x11
505#endif
506
507#define CONFIG_PCI_SCAN_SHOW
508
509#endif
510
511
512#define CONFIG_LIBATA
513#define CONFIG_FSL_SATA
514
515#define CONFIG_SYS_SATA_MAX_DEVICE 2
516#define CONFIG_SATA1
517#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
518#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
519#define CONFIG_SATA2
520#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
521#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
522
523#ifdef CONFIG_FSL_SATA
524#define CONFIG_LBA48
525#define CONFIG_CMD_SATA
526#endif
527
528#if defined(CONFIG_TSEC_ENET)
529
530#define CONFIG_MII 1
531#define CONFIG_MII_DEFAULT_TSEC 1
532#define CONFIG_TSEC1 1
533#define CONFIG_TSEC1_NAME "eTSEC1"
534#define CONFIG_TSEC3 1
535#define CONFIG_TSEC3_NAME "eTSEC3"
536
537#define CONFIG_FSL_SGMII_RISER 1
538#define SGMII_RISER_PHY_OFFSET 0x1c
539
540#define TSEC1_PHY_ADDR 1
541#define TSEC3_PHY_ADDR 0
542
543#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
544#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
545
546#define TSEC1_PHYIDX 0
547#define TSEC3_PHYIDX 0
548
549#define CONFIG_ETHPRIME "eTSEC1"
550
551#define CONFIG_PHY_GIGE 1
552
553#endif
554
555
556
557
558
559#if defined(CONFIG_SYS_RAMBOOT)
560#if defined(CONFIG_RAMBOOT_SPIFLASH)
561#define CONFIG_ENV_IS_IN_SPI_FLASH
562#define CONFIG_ENV_SPI_BUS 0
563#define CONFIG_ENV_SPI_CS 0
564#define CONFIG_ENV_SPI_MAX_HZ 10000000
565#define CONFIG_ENV_SPI_MODE 0
566#define CONFIG_ENV_SIZE 0x2000
567#define CONFIG_ENV_OFFSET 0xF0000
568#define CONFIG_ENV_SECT_SIZE 0x10000
569#elif defined(CONFIG_RAMBOOT_SDCARD)
570#define CONFIG_ENV_IS_IN_MMC
571#define CONFIG_FSL_FIXED_MMC_LOCATION
572#define CONFIG_ENV_SIZE 0x2000
573#define CONFIG_SYS_MMC_ENV_DEV 0
574#else
575 #define CONFIG_ENV_IS_NOWHERE 1
576 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
577 #define CONFIG_ENV_SIZE 0x2000
578#endif
579#else
580 #define CONFIG_ENV_IS_IN_FLASH 1
581 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
582 #define CONFIG_ENV_SIZE 0x2000
583 #define CONFIG_ENV_SECT_SIZE 0x20000
584#endif
585
586#define CONFIG_LOADS_ECHO 1
587#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
588
589
590
591
592#define CONFIG_CMD_REGINFO
593
594#if defined(CONFIG_PCI)
595#define CONFIG_CMD_PCI
596#endif
597
598#undef CONFIG_WATCHDOG
599
600#ifdef CONFIG_MMC
601#define CONFIG_FSL_ESDHC
602#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
603#endif
604
605
606
607
608#define CONFIG_HAS_FSL_MPH_USB
609#ifdef CONFIG_HAS_FSL_MPH_USB
610#ifdef CONFIG_USB_EHCI_HCD
611#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
612#define CONFIG_USB_EHCI_FSL
613#endif
614#endif
615
616
617
618
619#define CONFIG_SYS_LONGHELP
620#define CONFIG_CMDLINE_EDITING
621#define CONFIG_AUTO_COMPLETE
622#define CONFIG_SYS_LOAD_ADDR 0x2000000
623#if defined(CONFIG_CMD_KGDB)
624#define CONFIG_SYS_CBSIZE 1024
625#else
626#define CONFIG_SYS_CBSIZE 256
627#endif
628#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
629 + sizeof(CONFIG_SYS_PROMPT) + 16)
630#define CONFIG_SYS_MAXARGS 16
631#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
632
633
634
635
636
637
638#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
639#define CONFIG_SYS_BOOTM_LEN (64 << 20)
640
641#if defined(CONFIG_CMD_KGDB)
642#define CONFIG_KGDB_BAUDRATE 230400
643#endif
644
645
646
647
648
649
650#if defined(CONFIG_TSEC_ENET)
651#define CONFIG_HAS_ETH0
652#define CONFIG_HAS_ETH1
653#define CONFIG_HAS_ETH2
654#define CONFIG_HAS_ETH3
655#endif
656
657#define CONFIG_IPADDR 192.168.1.254
658
659#define CONFIG_HOSTNAME unknown
660#define CONFIG_ROOTPATH "/opt/nfsroot"
661#define CONFIG_BOOTFILE "uImage"
662#define CONFIG_UBOOTPATH u-boot.bin
663
664#define CONFIG_SERVERIP 192.168.1.1
665#define CONFIG_GATEWAYIP 192.168.1.1
666#define CONFIG_NETMASK 255.255.255.0
667
668
669#define CONFIG_LOADADDR 1000000
670
671#undef CONFIG_BOOTARGS
672
673#define CONFIG_EXTRA_ENV_SETTINGS \
674"netdev=eth0\0" \
675"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
676"tftpflash=tftpboot $loadaddr $uboot; " \
677 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
678 " +$filesize; " \
679 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
680 " +$filesize; " \
681 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
682 " $filesize; " \
683 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
684 " +$filesize; " \
685 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
686 " $filesize\0" \
687"consoledev=ttyS0\0" \
688"ramdiskaddr=2000000\0" \
689"ramdiskfile=8536ds/ramdisk.uboot\0" \
690"fdtaddr=1e00000\0" \
691"fdtfile=8536ds/mpc8536ds.dtb\0" \
692"bdev=sda3\0" \
693"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
694
695#define CONFIG_HDBOOT \
696 "setenv bootargs root=/dev/$bdev rw " \
697 "console=$consoledev,$baudrate $othbootargs;" \
698 "tftp $loadaddr $bootfile;" \
699 "tftp $fdtaddr $fdtfile;" \
700 "bootm $loadaddr - $fdtaddr"
701
702#define CONFIG_NFSBOOTCOMMAND \
703 "setenv bootargs root=/dev/nfs rw " \
704 "nfsroot=$serverip:$rootpath " \
705 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
706 "console=$consoledev,$baudrate $othbootargs;" \
707 "tftp $loadaddr $bootfile;" \
708 "tftp $fdtaddr $fdtfile;" \
709 "bootm $loadaddr - $fdtaddr"
710
711#define CONFIG_RAMBOOTCOMMAND \
712 "setenv bootargs root=/dev/ram rw " \
713 "console=$consoledev,$baudrate $othbootargs;" \
714 "tftp $ramdiskaddr $ramdiskfile;" \
715 "tftp $loadaddr $bootfile;" \
716 "tftp $fdtaddr $fdtfile;" \
717 "bootm $loadaddr $ramdiskaddr $fdtaddr"
718
719#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
720
721#endif
722