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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#ifndef CONFIG_SYS_TEXT_BASE
15#define CONFIG_SYS_TEXT_BASE 0xfff80000
16#endif
17
18#define CONFIG_PCI1 1
19#define CONFIG_PCIE1 1
20#define CONFIG_PCIE2 1
21#define CONFIG_PCIE3 1
22#define CONFIG_FSL_PCI_INIT 1
23#define CONFIG_PCI_INDIRECT_BRIDGE 1
24#define CONFIG_FSL_PCIE_RESET 1
25#define CONFIG_SYS_PCI_64BIT 1
26
27#define CONFIG_TSEC_ENET
28#define CONFIG_ENV_OVERWRITE
29#define CONFIG_INTERRUPTS
30
31#ifndef __ASSEMBLY__
32extern unsigned long get_board_sys_clk(unsigned long dummy);
33#endif
34#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
35
36
37
38
39#define CONFIG_L2_CACHE
40#define CONFIG_BTB
41
42
43
44
45#define CONFIG_ENABLE_36BIT_PHYS 1
46
47#define CONFIG_SYS_MEMTEST_START 0x00200000
48#define CONFIG_SYS_MEMTEST_END 0x00400000
49#define CONFIG_PANIC_HANG
50
51#define CONFIG_SYS_CCSRBAR 0xe0000000
52#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
53
54
55#undef CONFIG_FSL_DDR_INTERACTIVE
56#define CONFIG_SPD_EEPROM
57#define CONFIG_DDR_SPD
58
59#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
60#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
61
62#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
63#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
64#define CONFIG_VERY_BIG_RAM
65
66#define CONFIG_DIMM_SLOTS_PER_CTLR 1
67#define CONFIG_CHIP_SELECTS_PER_CTRL 2
68
69
70#define SPD_EEPROM_ADDRESS 0x51
71
72
73#ifndef CONFIG_SPD_EEPROM
74#error ("CONFIG_SPD_EEPROM is required")
75#endif
76
77#undef CONFIG_CLOCKS_IN_MHZ
78
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105
106
107#define CONFIG_SYS_BOOT_BLOCK 0xfc000000
108
109#define CONFIG_SYS_FLASH_BASE 0xff800000
110
111#define CONFIG_SYS_BR0_PRELIM 0xff801001
112#define CONFIG_SYS_BR1_PRELIM 0xfe801001
113
114#define CONFIG_SYS_OR0_PRELIM 0xff806e65
115#define CONFIG_SYS_OR1_PRELIM 0xff806e65
116
117#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
118
119#define CONFIG_SYS_FLASH_QUIET_TEST
120#define CONFIG_SYS_MAX_FLASH_BANKS 1
121#define CONFIG_SYS_MAX_FLASH_SECT 128
122#undef CONFIG_SYS_FLASH_CHECKSUM
123#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
124#define CONFIG_SYS_FLASH_WRITE_TOUT 500
125#define CONFIG_FLASH_SHOW_PROGRESS 45
126
127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
128
129#define CONFIG_FLASH_CFI_DRIVER
130#define CONFIG_SYS_FLASH_CFI
131#define CONFIG_SYS_FLASH_EMPTY_INFO
132
133#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
134
135#define CONFIG_SYS_BR2_PRELIM 0xf8201001
136#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7
137
138#define CONFIG_SYS_BR3_PRELIM 0xf8100801
139#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7
140
141#define CONFIG_FSL_PIXIS 1
142#define PIXIS_BASE 0xf8100000
143#define PIXIS_ID 0x0
144#define PIXIS_VER 0x1
145#define PIXIS_PVER 0x2
146#define PIXIS_RST 0x4
147#define PIXIS_AUX 0x6
148
149#define PIXIS_SPD 0x7
150#define PIXIS_VCTL 0x10
151#define PIXIS_VCFGEN0 0x12
152#define PIXIS_VCFGEN1 0x13
153#define PIXIS_VBOOT 0x16
154#define PIXIS_VBOOT_FMAP 0x80
155#define PIXIS_VBOOT_FBANK 0x40
156#define PIXIS_VSPEED0 0x17
157#define PIXIS_VSPEED1 0x18
158#define PIXIS_VCLKH 0x19
159#define PIXIS_VCLKL 0x1A
160#define PIXIS_VSPEED2 0x1d
161#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40
162#define PIXIS_VSPEED2_TSEC1SER 0x2
163#define PIXIS_VSPEED2_TSEC3SER 0x1
164#define PIXIS_VCFGEN1_TSEC1SER 0x20
165#define PIXIS_VCFGEN1_TSEC3SER 0x40
166#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
167#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
168
169#define CONFIG_SYS_INIT_RAM_LOCK 1
170#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000
171#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
172
173#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
174#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
175
176#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
177#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
178
179
180
181
182
183#define CONFIG_CONS_INDEX 1
184#define CONFIG_SYS_NS16550_SERIAL
185#define CONFIG_SYS_NS16550_REG_SIZE 1
186#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
187
188#define CONFIG_SYS_BAUDRATE_TABLE \
189 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
190
191#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
192#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
193
194
195#define CONFIG_SYS_I2C
196#define CONFIG_SYS_I2C_FSL
197#define CONFIG_SYS_FSL_I2C_SPEED 400000
198#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
199#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
200#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
201#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
202
203
204
205
206
207#define CONFIG_SYS_PCIE_VIRT 0x80000000
208#define CONFIG_SYS_PCIE_PHYS 0x80000000
209#define CONFIG_SYS_PCI_VIRT 0xc0000000
210#define CONFIG_SYS_PCI_PHYS 0xc0000000
211
212#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
213#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
214#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
215#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
216#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
217#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
218#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
219#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000
220
221
222#define CONFIG_SYS_PCIE2_NAME "Slot 1"
223#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
224#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
225#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
226#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
227#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
228#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
229#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
230#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
231
232
233#define CONFIG_SYS_PCIE1_NAME "Slot 2"
234#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
235#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
236#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
237#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
238#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
239#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
240#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
241#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
242
243
244#define CONFIG_SYS_PCIE3_NAME "ULI"
245#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
246#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
247#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
248#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000
249#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000
250#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
251#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000
252#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000
253#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
254#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
255#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
256#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000
257
258#if defined(CONFIG_PCI)
259
260
261#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
262
263
264
265
266
267
268#if defined(CONFIG_VIDEO)
269#define CONFIG_BIOSEMU
270#define CONFIG_ATI_RADEON_FB
271#define CONFIG_VIDEO_LOGO
272#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
273#endif
274
275#undef CONFIG_EEPRO100
276#undef CONFIG_TULIP
277
278#ifndef CONFIG_PCI_PNP
279 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
280 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
281 #define PCI_IDSEL_NUMBER 0x11
282#endif
283
284#define CONFIG_PCI_SCAN_SHOW
285#define CONFIG_SCSI_AHCI
286
287#ifdef CONFIG_SCSI_AHCI
288#define CONFIG_LIBATA
289#define CONFIG_SATA_ULI5288
290#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
291#define CONFIG_SYS_SCSI_MAX_LUN 1
292#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
293#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
294#endif
295
296#endif
297
298#if defined(CONFIG_TSEC_ENET)
299
300#define CONFIG_MII 1
301#define CONFIG_MII_DEFAULT_TSEC 1
302#define CONFIG_TSEC1 1
303#define CONFIG_TSEC1_NAME "eTSEC1"
304#define CONFIG_TSEC3 1
305#define CONFIG_TSEC3_NAME "eTSEC3"
306
307#define CONFIG_PIXIS_SGMII_CMD
308#define CONFIG_FSL_SGMII_RISER 1
309#define SGMII_RISER_PHY_OFFSET 0x1c
310
311#define TSEC1_PHY_ADDR 0
312#define TSEC3_PHY_ADDR 1
313
314#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
315#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
316
317#define TSEC1_PHYIDX 0
318#define TSEC3_PHYIDX 0
319
320#define CONFIG_ETHPRIME "eTSEC1"
321
322#define CONFIG_PHY_GIGE 1
323#endif
324
325
326
327
328#define CONFIG_ENV_IS_IN_FLASH 1
329#define CONFIG_ENV_SECT_SIZE 0x10000
330#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
331#define CONFIG_ENV_ADDR 0xfff80000
332#else
333#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
334#endif
335#define CONFIG_ENV_SIZE 0x2000
336
337#define CONFIG_LOADS_ECHO 1
338#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
339
340
341
342
343#define CONFIG_BOOTP_BOOTFILESIZE
344#define CONFIG_BOOTP_BOOTPATH
345#define CONFIG_BOOTP_GATEWAY
346#define CONFIG_BOOTP_HOSTNAME
347
348
349
350
351#define CONFIG_CMD_REGINFO
352
353#if defined(CONFIG_PCI)
354 #define CONFIG_CMD_PCI
355 #define CONFIG_SCSI
356#endif
357
358
359
360
361
362#ifdef CONFIG_USB_EHCI_HCD
363#define CONFIG_USB_EHCI_PCI
364#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
365#define CONFIG_PCI_EHCI_DEVICE 0
366#endif
367
368#undef CONFIG_WATCHDOG
369
370
371
372
373#define CONFIG_SYS_LONGHELP
374#define CONFIG_CMDLINE_EDITING
375#define CONFIG_AUTO_COMPLETE
376#define CONFIG_SYS_LOAD_ADDR 0x2000000
377#if defined(CONFIG_CMD_KGDB)
378#define CONFIG_SYS_CBSIZE 1024
379#else
380#define CONFIG_SYS_CBSIZE 256
381#endif
382#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
383#define CONFIG_SYS_MAXARGS 16
384#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
385
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387
388
389
390
391#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
392#define CONFIG_SYS_BOOTM_LEN (64 << 20)
393
394#if defined(CONFIG_CMD_KGDB)
395#define CONFIG_KGDB_BAUDRATE 230400
396#endif
397
398
399
400
401
402
403#if defined(CONFIG_TSEC_ENET)
404#define CONFIG_HAS_ETH0
405#define CONFIG_HAS_ETH1
406#endif
407
408#define CONFIG_IPADDR 192.168.1.251
409
410#define CONFIG_HOSTNAME 8544ds_unknown
411#define CONFIG_ROOTPATH "/nfs/mpc85xx"
412#define CONFIG_BOOTFILE "8544ds/uImage.uboot"
413#define CONFIG_UBOOTPATH 8544ds/u-boot.bin
414
415#define CONFIG_SERVERIP 192.168.1.1
416#define CONFIG_GATEWAYIP 192.168.1.1
417#define CONFIG_NETMASK 255.255.0.0
418
419#define CONFIG_LOADADDR 1000000
420
421#undef CONFIG_BOOTARGS
422
423#define CONFIG_EXTRA_ENV_SETTINGS \
424"netdev=eth0\0" \
425"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
426"tftpflash=tftpboot $loadaddr $uboot; " \
427 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
428 " +$filesize; " \
429 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
430 " +$filesize; " \
431 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
432 " $filesize; " \
433 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
434 " +$filesize; " \
435 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
436 " $filesize\0" \
437"consoledev=ttyS0\0" \
438"ramdiskaddr=2000000\0" \
439"ramdiskfile=8544ds/ramdisk.uboot\0" \
440"fdtaddr=1e00000\0" \
441"fdtfile=8544ds/mpc8544ds.dtb\0" \
442"bdev=sda3\0"
443
444#define CONFIG_NFSBOOTCOMMAND \
445 "setenv bootargs root=/dev/nfs rw " \
446 "nfsroot=$serverip:$rootpath " \
447 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
448 "console=$consoledev,$baudrate $othbootargs;" \
449 "tftp $loadaddr $bootfile;" \
450 "tftp $fdtaddr $fdtfile;" \
451 "bootm $loadaddr - $fdtaddr"
452
453#define CONFIG_RAMBOOTCOMMAND \
454 "setenv bootargs root=/dev/ram rw " \
455 "console=$consoledev,$baudrate $othbootargs;" \
456 "tftp $ramdiskaddr $ramdiskfile;" \
457 "tftp $loadaddr $bootfile;" \
458 "tftp $fdtaddr $fdtfile;" \
459 "bootm $loadaddr $ramdiskaddr $fdtaddr"
460
461#define CONFIG_BOOTCOMMAND \
462 "setenv bootargs root=/dev/$bdev rw " \
463 "console=$consoledev,$baudrate $othbootargs;" \
464 "tftp $loadaddr $bootfile;" \
465 "tftp $fdtaddr $fdtfile;" \
466 "bootm $loadaddr - $fdtaddr"
467
468#endif
469