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13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16
17#define CONFIG_CPM2 1
18
19#define CONFIG_SYS_TEXT_BASE 0xfff80000
20
21#define CONFIG_PCI_INDIRECT_BRIDGE
22#define CONFIG_SYS_PCI_64BIT 1
23#define CONFIG_TSEC_ENET
24#define CONFIG_ENV_OVERWRITE
25
26#define CONFIG_FSL_VIA
27
28#ifndef __ASSEMBLY__
29extern unsigned long get_clock_freq(void);
30#endif
31#define CONFIG_SYS_CLK_FREQ get_clock_freq()
32
33
34
35
36#define CONFIG_L2_CACHE
37#define CONFIG_BTB
38
39#define CONFIG_SYS_MEMTEST_START 0x00200000
40#define CONFIG_SYS_MEMTEST_END 0x00400000
41
42#define CONFIG_SYS_CCSRBAR 0xe0000000
43#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
44
45
46#define CONFIG_SPD_EEPROM
47#define CONFIG_DDR_SPD
48#undef CONFIG_FSL_DDR_INTERACTIVE
49
50#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
51
52#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
53#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
54
55#define CONFIG_DIMM_SLOTS_PER_CTLR 1
56#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
57
58
59#define SPD_EEPROM_ADDRESS 0x51
60
61
62#ifndef CONFIG_SPD_EEPROM
63#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
64#endif
65
66#undef CONFIG_CLOCKS_IN_MHZ
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101
102#define CONFIG_SYS_FLASH_BASE 0xff000000
103
104#define CONFIG_SYS_BR0_PRELIM 0xff801001
105#define CONFIG_SYS_BR1_PRELIM 0xff001001
106
107#define CONFIG_SYS_OR0_PRELIM 0xff806e65
108#define CONFIG_SYS_OR1_PRELIM 0xff806e65
109
110#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
111#define CONFIG_SYS_MAX_FLASH_BANKS 2
112#define CONFIG_SYS_MAX_FLASH_SECT 128
113#undef CONFIG_SYS_FLASH_CHECKSUM
114#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
115#define CONFIG_SYS_FLASH_WRITE_TOUT 500
116
117#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
118
119#define CONFIG_FLASH_CFI_DRIVER
120#define CONFIG_SYS_FLASH_CFI
121#define CONFIG_SYS_FLASH_EMPTY_INFO
122
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125
126#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
127#define CONFIG_SYS_LBC_SDRAM_SIZE 64
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147#define CONFIG_SYS_BR2_PRELIM 0xf0001861
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163#define CONFIG_SYS_OR2_PRELIM 0xfc006901
164
165#define CONFIG_SYS_LBC_LCRR 0x00030004
166#define CONFIG_SYS_LBC_LBCR 0x00000000
167#define CONFIG_SYS_LBC_LSRT 0x20000000
168#define CONFIG_SYS_LBC_MRTPR 0x00000000
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175
176#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
177 | LSDMR_PRETOACT7 \
178 | LSDMR_ACTTORW7 \
179 | LSDMR_BL8 \
180 | LSDMR_WRC4 \
181 | LSDMR_CL3 \
182 | LSDMR_RFEN \
183 )
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214
215#define CONFIG_FSL_CADMUS
216
217#define CADMUS_BASE_ADDR 0xf8000000
218#define CONFIG_SYS_BR3_PRELIM 0xf8000801
219#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
220
221#define CONFIG_SYS_INIT_RAM_LOCK 1
222#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
223#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
224
225#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
226#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
227
228#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
229#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
230
231
232#define CONFIG_CONS_INDEX 2
233#define CONFIG_SYS_NS16550_SERIAL
234#define CONFIG_SYS_NS16550_REG_SIZE 1
235#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
236
237#define CONFIG_SYS_BAUDRATE_TABLE \
238 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
239
240#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
241#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
242
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245
246#define CONFIG_SYS_I2C
247#define CONFIG_SYS_I2C_FSL
248#define CONFIG_SYS_FSL_I2C_SPEED 400000
249#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
250#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
251#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
252
253
254#define CONFIG_ID_EEPROM
255#define CONFIG_SYS_I2C_EEPROM_CCID
256#define CONFIG_SYS_ID_EEPROM
257#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
258#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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264#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
265#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
266#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
267#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
268#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
269#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
270#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
271#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
272
273#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
274#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
275#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
276#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000
277#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
278#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
279#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
280#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
281
282#ifdef CONFIG_LEGACY
283#define BRIDGE_ID 17
284#define VIA_ID 2
285#else
286#define BRIDGE_ID 28
287#define VIA_ID 4
288#endif
289
290#if defined(CONFIG_PCI)
291
292#define CONFIG_MPC85XX_PCI2
293
294#undef CONFIG_EEPRO100
295#undef CONFIG_TULIP
296
297#define CONFIG_PCI_SCAN_SHOW
298#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
299
300#endif
301
302#if defined(CONFIG_TSEC_ENET)
303
304#define CONFIG_MII 1
305#define CONFIG_TSEC1 1
306#define CONFIG_TSEC1_NAME "TSEC0"
307#define CONFIG_TSEC2 1
308#define CONFIG_TSEC2_NAME "TSEC1"
309#define TSEC1_PHY_ADDR 0
310#define TSEC2_PHY_ADDR 1
311#define TSEC1_PHYIDX 0
312#define TSEC2_PHYIDX 0
313#define TSEC1_FLAGS TSEC_GIGABIT
314#define TSEC2_FLAGS TSEC_GIGABIT
315
316
317#define CONFIG_ETHPRIME "TSEC0"
318
319#endif
320
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323
324#define CONFIG_ENV_IS_IN_FLASH 1
325#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
326#define CONFIG_ENV_SECT_SIZE 0x40000
327#define CONFIG_ENV_SIZE 0x2000
328
329#define CONFIG_LOADS_ECHO 1
330#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
331
332
333
334
335#define CONFIG_BOOTP_BOOTFILESIZE
336#define CONFIG_BOOTP_BOOTPATH
337#define CONFIG_BOOTP_GATEWAY
338#define CONFIG_BOOTP_HOSTNAME
339
340
341
342
343#define CONFIG_CMD_REGINFO
344
345#if defined(CONFIG_PCI)
346 #define CONFIG_CMD_PCI
347#endif
348
349#undef CONFIG_WATCHDOG
350
351
352
353
354#define CONFIG_SYS_LONGHELP
355#define CONFIG_CMDLINE_EDITING
356#define CONFIG_AUTO_COMPLETE
357#define CONFIG_SYS_LOAD_ADDR 0x2000000
358#if defined(CONFIG_CMD_KGDB)
359#define CONFIG_SYS_CBSIZE 1024
360#else
361#define CONFIG_SYS_CBSIZE 256
362#endif
363#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
364#define CONFIG_SYS_MAXARGS 16
365#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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371
372#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
373#define CONFIG_SYS_BOOTM_LEN (64 << 20)
374
375#if defined(CONFIG_CMD_KGDB)
376#define CONFIG_KGDB_BAUDRATE 230400
377#endif
378
379
380
381
382#if defined(CONFIG_TSEC_ENET)
383#define CONFIG_HAS_ETH0
384#define CONFIG_HAS_ETH1
385#define CONFIG_HAS_ETH2
386#endif
387
388#define CONFIG_IPADDR 192.168.1.253
389
390#define CONFIG_HOSTNAME unknown
391#define CONFIG_ROOTPATH "/nfsroot"
392#define CONFIG_BOOTFILE "your.uImage"
393
394#define CONFIG_SERVERIP 192.168.1.1
395#define CONFIG_GATEWAYIP 192.168.1.1
396#define CONFIG_NETMASK 255.255.255.0
397
398#define CONFIG_LOADADDR 200000
399
400#undef CONFIG_BOOTARGS
401
402#define CONFIG_EXTRA_ENV_SETTINGS \
403 "netdev=eth0\0" \
404 "consoledev=ttyS1\0" \
405 "ramdiskaddr=600000\0" \
406 "ramdiskfile=your.ramdisk.u-boot\0" \
407 "fdtaddr=400000\0" \
408 "fdtfile=your.fdt.dtb\0"
409
410#define CONFIG_NFSBOOTCOMMAND \
411 "setenv bootargs root=/dev/nfs rw " \
412 "nfsroot=$serverip:$rootpath " \
413 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
414 "console=$consoledev,$baudrate $othbootargs;" \
415 "tftp $loadaddr $bootfile;" \
416 "tftp $fdtaddr $fdtfile;" \
417 "bootm $loadaddr - $fdtaddr"
418
419#define CONFIG_RAMBOOTCOMMAND \
420 "setenv bootargs root=/dev/ram rw " \
421 "console=$consoledev,$baudrate $othbootargs;" \
422 "tftp $ramdiskaddr $ramdiskfile;" \
423 "tftp $loadaddr $bootfile;" \
424 "bootm $loadaddr $ramdiskaddr"
425
426#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
427
428#endif
429