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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_SYS_SRIO
14#define CONFIG_SRIO1
15
16#define CONFIG_PCIE1 1
17#define CONFIG_FSL_PCI_INIT 1
18#define CONFIG_PCI_INDIRECT_BRIDGE 1
19#define CONFIG_FSL_PCIE_RESET 1
20#define CONFIG_SYS_PCI_64BIT 1
21#define CONFIG_QE
22#define CONFIG_ENV_OVERWRITE
23
24#ifndef __ASSEMBLY__
25extern unsigned long get_clock_freq(void);
26#endif
27
28#define CONFIG_SYS_CLK_FREQ 66666666
29#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
30
31#ifdef CONFIG_ATM
32#define CONFIG_PQ_MDS_PIB
33#define CONFIG_PQ_MDS_PIB_ATM
34#endif
35
36
37
38
39#define CONFIG_L2_CACHE
40#define CONFIG_BTB
41
42#ifndef CONFIG_SYS_TEXT_BASE
43#define CONFIG_SYS_TEXT_BASE 0xfff80000
44#endif
45
46#ifndef CONFIG_SYS_MONITOR_BASE
47#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
48#endif
49
50
51
52
53#define CONFIG_ENABLE_36BIT_PHYS 1
54
55#define CONFIG_BOARD_EARLY_INIT_R 1
56#define CONFIG_HWCONFIG
57
58#define CONFIG_SYS_MEMTEST_START 0x00200000
59#define CONFIG_SYS_MEMTEST_END 0x00400000
60
61
62
63
64#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
65#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
66#define CONFIG_SYS_L2_SIZE (512 << 10)
67#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
68
69#define CONFIG_SYS_CCSRBAR 0xe0000000
70#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
71
72#if defined(CONFIG_NAND_SPL)
73#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
74#endif
75
76
77#undef CONFIG_FSL_DDR_INTERACTIVE
78#define CONFIG_SPD_EEPROM
79#define CONFIG_DDR_SPD
80#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
81
82#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
83
84#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
85
86#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
87
88#define CONFIG_DIMM_SLOTS_PER_CTLR 1
89#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
90
91
92#define SPD_EEPROM_ADDRESS 0x51
93
94
95#define CONFIG_SYS_SDRAM_SIZE 1024
96#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
97#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
98#define CONFIG_SYS_DDR_TIMING_3 0x00020000
99#define CONFIG_SYS_DDR_TIMING_0 0x00330004
100#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
101#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
102#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
103#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
104#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
105#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
106#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
107#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
108#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
109#define CONFIG_SYS_DDR_TIMING_4 0x00220001
110#define CONFIG_SYS_DDR_TIMING_5 0x03402400
111#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
112#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
113#define CONFIG_SYS_DDR_CDR_1 0x80040000
114#define CONFIG_SYS_DDR_CDR_2 0x00000000
115#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
116#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
117#define CONFIG_SYS_DDR_CONTROL 0xc7000000
118#define CONFIG_SYS_DDR_CONTROL2 0x24400000
119
120#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
121#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
122#define CONFIG_SYS_DDR_SBE 0x00010000
123
124#undef CONFIG_CLOCKS_IN_MHZ
125
126
127
128
129
130#define CONFIG_SYS_FLASH_BASE 0xfe000000
131#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
132
133#define CONFIG_SYS_BCSR_BASE 0xf8000000
134#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
135
136
137#define CONFIG_FLASH_BR_PRELIM 0xfe000801
138#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
139
140
141#define CONFIG_SYS_BR1_PRELIM 0xf8000801
142#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
143
144
145#define CONFIG_SYS_BR4_PRELIM 0xf8008801
146#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
147
148
149#define CONFIG_SYS_BR5_PRELIM 0xf8010801
150#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
151
152#define CONFIG_SYS_MAX_FLASH_BANKS 1
153#define CONFIG_SYS_MAX_FLASH_SECT 512
154#undef CONFIG_SYS_FLASH_CHECKSUM
155#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
156#define CONFIG_SYS_FLASH_WRITE_TOUT 500
157
158#undef CONFIG_SYS_RAMBOOT
159
160#define CONFIG_FLASH_CFI_DRIVER
161#define CONFIG_SYS_FLASH_CFI
162#define CONFIG_SYS_FLASH_EMPTY_INFO
163
164
165#ifndef CONFIG_NAND_SPL
166#define CONFIG_SYS_NAND_BASE 0xFC000000
167#else
168#define CONFIG_SYS_NAND_BASE 0xFFF00000
169#endif
170
171
172#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
173#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
174#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
175#define CONFIG_SYS_NAND_U_BOOT_START \
176 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
177#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
178#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
179#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
180
181#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
182#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
183#define CONFIG_SYS_MAX_NAND_DEVICE 1
184#define CONFIG_CMD_NAND 1
185#define CONFIG_NAND_FSL_ELBC 1
186#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
187#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
188 | (2<<BR_DECC_SHIFT) \
189 | BR_PS_8 \
190 | BR_MS_FCM \
191 | BR_V)
192#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
193 | OR_FCM_CSCT \
194 | OR_FCM_CST \
195 | OR_FCM_CHT \
196 | OR_FCM_SCY_1 \
197 | OR_FCM_TRLX \
198 | OR_FCM_EHTR)
199
200#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
201#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
202#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM
203#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM
204
205#define CONFIG_SYS_LBC_LCRR 0x00000004
206#define CONFIG_SYS_LBC_LBCR 0x00040000
207#define CONFIG_SYS_LBC_LSRT 0x20000000
208#define CONFIG_SYS_LBC_MRTPR 0x00000000
209
210#define CONFIG_SYS_INIT_RAM_LOCK 1
211#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
212#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
213
214#define CONFIG_SYS_GBL_DATA_OFFSET \
215 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
216#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
217
218#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
219#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
220
221
222#define CONFIG_CONS_INDEX 1
223#define CONFIG_SYS_NS16550_SERIAL
224#define CONFIG_SYS_NS16550_REG_SIZE 1
225#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
226#ifdef CONFIG_NAND_SPL
227#define CONFIG_NS16550_MIN_FUNCTIONS
228#endif
229
230#define CONFIG_SYS_BAUDRATE_TABLE \
231 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
232
233#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
234#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
235
236
237
238
239#define CONFIG_SYS_I2C
240#define CONFIG_SYS_I2C_FSL
241#define CONFIG_SYS_FSL_I2C_SPEED 400000
242#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
243#define CONFIG_SYS_FSL_I2C2_SPEED 400000
244#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
245#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
246#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
247#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
248
249
250
251
252#define CONFIG_ID_EEPROM
253#ifdef CONFIG_ID_EEPROM
254#define CONFIG_SYS_I2C_EEPROM_NXID
255#endif
256#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
257#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
258#define CONFIG_SYS_EEPROM_BUS_NUM 1
259
260#define PLPPAR1_I2C_BIT_MASK 0x0000000F
261#define PLPPAR1_I2C2_VAL 0x00000000
262#define PLPPAR1_ESDHC_VAL 0x0000000A
263#define PLPDIR1_I2C_BIT_MASK 0x0000000F
264#define PLPDIR1_I2C2_VAL 0x0000000F
265#define PLPDIR1_ESDHC_VAL 0x00000006
266#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
267#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
268#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
269#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
270
271
272
273
274
275#define CONFIG_SYS_PCIE1_NAME "Slot"
276#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
277#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
278#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
279#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
280#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
281#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
282#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
283#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
284
285#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
286#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
287#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
288#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
289
290#ifdef CONFIG_QE
291
292
293
294#define CONFIG_SYS_UCC_RGMII_MODE
295#undef CONFIG_SYS_UCC_RMII_MODE
296
297#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
298#define CONFIG_UEC_ETH
299#define CONFIG_ETHPRIME "UEC0"
300#define CONFIG_PHY_MODE_NEED_CHANGE
301
302#define CONFIG_UEC_ETH1
303#define CONFIG_HAS_ETH0
304
305#ifdef CONFIG_UEC_ETH1
306#define CONFIG_SYS_UEC1_UCC_NUM 0
307#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
308#if defined(CONFIG_SYS_UCC_RGMII_MODE)
309#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
310#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
311#define CONFIG_SYS_UEC1_PHY_ADDR 7
312#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
313#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
314#elif defined(CONFIG_SYS_UCC_RMII_MODE)
315#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
316#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
317#define CONFIG_SYS_UEC1_PHY_ADDR 8
318#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
319#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
320#endif
321#endif
322
323#define CONFIG_UEC_ETH2
324#define CONFIG_HAS_ETH1
325
326#ifdef CONFIG_UEC_ETH2
327#define CONFIG_SYS_UEC2_UCC_NUM 1
328#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
329#if defined(CONFIG_SYS_UCC_RGMII_MODE)
330#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
331#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
332#define CONFIG_SYS_UEC2_PHY_ADDR 1
333#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
334#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
335#elif defined(CONFIG_SYS_UCC_RMII_MODE)
336#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
337#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
338#define CONFIG_SYS_UEC2_PHY_ADDR 0x9
339#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
340#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
341#endif
342#endif
343
344#define CONFIG_UEC_ETH3
345#define CONFIG_HAS_ETH2
346
347#ifdef CONFIG_UEC_ETH3
348#define CONFIG_SYS_UEC3_UCC_NUM 2
349#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
350#if defined(CONFIG_SYS_UCC_RGMII_MODE)
351#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
352#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
353#define CONFIG_SYS_UEC3_PHY_ADDR 2
354#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
355#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
356#elif defined(CONFIG_SYS_UCC_RMII_MODE)
357#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16
358#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
359#define CONFIG_SYS_UEC3_PHY_ADDR 0xA
360#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
361#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
362#endif
363#endif
364
365#define CONFIG_UEC_ETH4
366#define CONFIG_HAS_ETH3
367
368#ifdef CONFIG_UEC_ETH4
369#define CONFIG_SYS_UEC4_UCC_NUM 3
370#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
371#if defined(CONFIG_SYS_UCC_RGMII_MODE)
372#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
373#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
374#define CONFIG_SYS_UEC4_PHY_ADDR 3
375#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
376#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
377#elif defined(CONFIG_SYS_UCC_RMII_MODE)
378#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16
379#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
380#define CONFIG_SYS_UEC4_PHY_ADDR 0xB
381#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
382#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
383#endif
384#endif
385
386#undef CONFIG_UEC_ETH6
387#define CONFIG_HAS_ETH5
388
389#ifdef CONFIG_UEC_ETH6
390#define CONFIG_SYS_UEC6_UCC_NUM 5
391#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
392#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
393#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
394#define CONFIG_SYS_UEC6_PHY_ADDR 4
395#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
396#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
397#endif
398
399#undef CONFIG_UEC_ETH8
400#define CONFIG_HAS_ETH7
401
402#ifdef CONFIG_UEC_ETH8
403#define CONFIG_SYS_UEC8_UCC_NUM 7
404#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
405#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
406#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
407#define CONFIG_SYS_UEC8_PHY_ADDR 6
408#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
409#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
410#endif
411
412#endif
413
414#if defined(CONFIG_PCI)
415#undef CONFIG_EEPRO100
416#undef CONFIG_TULIP
417
418#undef CONFIG_PCI_SCAN_SHOW
419
420#endif
421
422
423
424
425#if defined(CONFIG_SYS_RAMBOOT)
426#else
427#define CONFIG_ENV_IS_IN_FLASH 1
428#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
429#define CONFIG_ENV_SECT_SIZE 0x20000
430#define CONFIG_ENV_SIZE 0x2000
431#endif
432
433#define CONFIG_LOADS_ECHO 1
434#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
435
436
437#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
438#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
439
440
441
442
443#define CONFIG_BOOTP_BOOTFILESIZE
444#define CONFIG_BOOTP_BOOTPATH
445#define CONFIG_BOOTP_GATEWAY
446#define CONFIG_BOOTP_HOSTNAME
447
448
449
450
451#define CONFIG_CMD_REGINFO
452
453#if defined(CONFIG_PCI)
454 #define CONFIG_CMD_PCI
455#endif
456
457#undef CONFIG_WATCHDOG
458
459#ifdef CONFIG_MMC
460#define CONFIG_FSL_ESDHC
461#define CONFIG_FSL_ESDHC_PIN_MUX
462#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
463#endif
464
465
466
467
468#define CONFIG_SYS_LONGHELP
469#define CONFIG_CMDLINE_EDITING
470#define CONFIG_AUTO_COMPLETE
471#define CONFIG_SYS_LOAD_ADDR 0x2000000
472#if defined(CONFIG_CMD_KGDB)
473#define CONFIG_SYS_CBSIZE 2048
474#else
475#define CONFIG_SYS_CBSIZE 512
476#endif
477#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
478
479#define CONFIG_SYS_MAXARGS 32
480#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
481
482
483
484
485
486
487
488#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
489#define CONFIG_SYS_BOOTM_LEN (64 << 20)
490
491#if defined(CONFIG_CMD_KGDB)
492#define CONFIG_KGDB_BAUDRATE 230400
493#endif
494
495
496
497
498#define CONFIG_HOSTNAME mpc8569mds
499#define CONFIG_ROOTPATH "/nfsroot"
500#define CONFIG_BOOTFILE "your.uImage"
501
502#define CONFIG_SERVERIP 192.168.1.1
503#define CONFIG_GATEWAYIP 192.168.1.1
504#define CONFIG_NETMASK 255.255.255.0
505
506#define CONFIG_LOADADDR 200000
507
508#undef CONFIG_BOOTARGS
509
510#define CONFIG_EXTRA_ENV_SETTINGS \
511 "netdev=eth0\0" \
512 "consoledev=ttyS0\0" \
513 "ramdiskaddr=600000\0" \
514 "ramdiskfile=your.ramdisk.u-boot\0" \
515 "fdtaddr=400000\0" \
516 "fdtfile=your.fdt.dtb\0" \
517 "nfsargs=setenv bootargs root=/dev/nfs rw " \
518 "nfsroot=$serverip:$rootpath " \
519 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
520 "console=$consoledev,$baudrate $othbootargs\0" \
521 "ramargs=setenv bootargs root=/dev/ram rw " \
522 "console=$consoledev,$baudrate $othbootargs\0" \
523
524#define CONFIG_NFSBOOTCOMMAND \
525 "run nfsargs;" \
526 "tftp $loadaddr $bootfile;" \
527 "tftp $fdtaddr $fdtfile;" \
528 "bootm $loadaddr - $fdtaddr"
529
530#define CONFIG_RAMBOOTCOMMAND \
531 "run ramargs;" \
532 "tftp $ramdiskaddr $ramdiskfile;" \
533 "tftp $loadaddr $bootfile;" \
534 "bootm $loadaddr $ramdiskaddr"
535
536#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
537
538#endif
539