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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14
15#define CONFIG_LINUX_RESET_VEC 0x100
16
17#define CONFIG_SYS_TEXT_BASE 0xfff00000
18
19
20#define CONFIG_FSL_DIU_FB
21
22#ifdef CONFIG_FSL_DIU_FB
23#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
24#define CONFIG_VIDEO_LOGO
25#define CONFIG_VIDEO_BMP_LOGO
26#endif
27
28#ifdef RUN_DIAG
29#define CONFIG_SYS_DIAG_ADDR 0xff800000
30#endif
31
32
33
34
35
36#define CONFIG_SYS_SCRATCH_VA 0xc0000000
37
38#define CONFIG_PCI1 1
39#define CONFIG_PCIE1 1
40#define CONFIG_PCIE2 1
41#define CONFIG_FSL_PCI_INIT 1
42#define CONFIG_PCI_INDIRECT_BRIDGE 1
43#define CONFIG_SYS_PCI_64BIT 1
44
45#define CONFIG_ENV_OVERWRITE
46#define CONFIG_INTERRUPTS
47
48#define CONFIG_BAT_RW 1
49#define CONFIG_HIGH_BATS 1
50#define CONFIG_ALTIVEC 1
51
52
53
54
55#define CONFIG_SYS_L2
56#define L2_INIT 0
57#define L2_ENABLE (L2CR_L2E |0x00100000 )
58
59#ifndef CONFIG_SYS_CLK_FREQ
60#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
61#endif
62
63#define CONFIG_MISC_INIT_R 1
64
65#define CONFIG_SYS_MEMTEST_START 0x00200000
66#define CONFIG_SYS_MEMTEST_END 0x00400000
67
68
69
70
71
72#define CONFIG_SYS_CCSRBAR 0xe0000000
73#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
74
75#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
76#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
77#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
78
79
80#undef CONFIG_FSL_DDR_INTERACTIVE
81#define CONFIG_SPD_EEPROM
82#define CONFIG_DDR_SPD
83
84#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
85#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
86
87#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
88#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
89#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000
90#define CONFIG_VERY_BIG_RAM
91
92#define CONFIG_DIMM_SLOTS_PER_CTLR 1
93#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
94
95#define SPD_EEPROM_ADDRESS 0x51
96
97
98#define CONFIG_SYS_SDRAM_SIZE 256
99
100#if 0
101#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
102#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202
103#define CONFIG_SYS_DDR_TIMING_3 0x00000000
104#define CONFIG_SYS_DDR_TIMING_0 0x00260802
105#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
106#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
107#define CONFIG_SYS_DDR_MODE_1 0x00480432
108#define CONFIG_SYS_DDR_MODE_2 0x00000000
109#define CONFIG_SYS_DDR_INTERVAL 0x06180100
110#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
111#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
112#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
113#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
114#define CONFIG_SYS_DDR_CONTROL 0xe3008000
115#define CONFIG_SYS_DDR_CONTROL2 0x04400010
116
117#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
118#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
119#define CONFIG_SYS_DDR_SBE 0x000f0000
120
121#endif
122
123#define CONFIG_ID_EEPROM
124#define CONFIG_SYS_I2C_EEPROM_NXID
125#define CONFIG_ID_EEPROM
126#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
127#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
128
129#define CONFIG_SYS_FLASH_BASE 0xf0000000
130#define CONFIG_SYS_FLASH_BASE2 0xf8000000
131
132#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
133
134#define CONFIG_SYS_BR0_PRELIM 0xf8001001
135#define CONFIG_SYS_OR0_PRELIM 0xf8006e65
136
137#define CONFIG_SYS_BR1_PRELIM 0xf0001001
138#define CONFIG_SYS_OR1_PRELIM 0xf8006e65
139#if 0
140#define CONFIG_SYS_BR2_PRELIM 0xf0000000
141#define CONFIG_SYS_OR2_PRELIM 0xf0000000
142#endif
143#define CONFIG_SYS_BR3_PRELIM 0xe8000801
144#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7
145
146#define CONFIG_FSL_PIXIS 1
147#define PIXIS_BASE 0xe8000000
148#define PIXIS_ID 0x0
149#define PIXIS_VER 0x1
150#define PIXIS_PVER 0x2
151#define PIXIS_RST 0x4
152#define PIXIS_AUX 0x6
153#define PIXIS_SPD 0x7
154#define PIXIS_BRDCFG0 0x8
155#define PIXIS_VCTL 0x10
156#define PIXIS_VCFGEN0 0x12
157#define PIXIS_VCFGEN1 0x13
158#define PIXIS_VBOOT 0x16
159#define PIXIS_VSPEED0 0x17
160#define PIXIS_VSPEED1 0x18
161#define PIXIS_VCLKH 0x19
162#define PIXIS_VCLKL 0x1A
163#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0
164
165#define CONFIG_SYS_MAX_FLASH_BANKS 2
166#define CONFIG_SYS_MAX_FLASH_SECT 1024
167
168#undef CONFIG_SYS_FLASH_CHECKSUM
169#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
170#define CONFIG_SYS_FLASH_WRITE_TOUT 500
171#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
172#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000
173
174#define CONFIG_FLASH_CFI_DRIVER
175#define CONFIG_SYS_FLASH_CFI
176#define CONFIG_SYS_FLASH_EMPTY_INFO
177
178#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
179#define CONFIG_SYS_RAMBOOT
180#else
181#undef CONFIG_SYS_RAMBOOT
182#endif
183
184#if defined(CONFIG_SYS_RAMBOOT)
185#undef CONFIG_SPD_EEPROM
186#define CONFIG_SYS_SDRAM_SIZE 256
187#endif
188
189#undef CONFIG_CLOCKS_IN_MHZ
190
191#define CONFIG_SYS_INIT_RAM_LOCK 1
192#ifndef CONFIG_SYS_INIT_RAM_LOCK
193#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
194#else
195#define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000
196#endif
197#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
198
199#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
200#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
201
202#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
203#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
204
205
206#define CONFIG_CONS_INDEX 1
207#define CONFIG_SYS_NS16550_SERIAL
208#define CONFIG_SYS_NS16550_REG_SIZE 1
209#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
210
211#define CONFIG_SYS_BAUDRATE_TABLE \
212 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
213
214#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
215#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
216
217
218#define OF_FLAT_TREE_MAX_SIZE 8192
219
220
221
222
223#define CONFIG_SYS_I2C
224#define CONFIG_SYS_I2C_FSL
225#define CONFIG_SYS_FSL_I2C_SPEED 400000
226#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
227#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
228#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
229
230
231
232
233
234#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
235#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
236#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
237#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
238#define CONFIG_SYS_PCI1_IO_BUS 0x0000000
239#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
240#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
241#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
242
243
244#define CONFIG_SYS_PCIE1_NAME "ULI"
245#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
246#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
247#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
248#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
249#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
250#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000
251
252
253#define CONFIG_SYS_PCIE2_NAME "Slot 1"
254#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
255#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
256#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
257#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
258#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
259#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000
260
261#if defined(CONFIG_PCI)
262
263#define CONFIG_PCI_SCAN_SHOW
264
265#define CONFIG_CMD_REGINFO
266
267#define CONFIG_ULI526X
268#ifdef CONFIG_ULI526X
269#endif
270
271
272
273
274#define CONFIG_PCI_OHCI 1
275#define CONFIG_USB_OHCI_NEW 1
276#define CONFIG_SYS_USB_EVENT_POLL 1
277#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
278#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
279#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
280
281#if !defined(CONFIG_PCI_PNP)
282#define PCI_ENET0_IOADDR 0xe0000000
283#define PCI_ENET0_MEMADDR 0xe0000000
284#define PCI_IDSEL_NUMBER 0x0c
285#endif
286
287#define CONFIG_SCSI_AHCI
288
289#ifdef CONFIG_SCSI_AHCI
290#define CONFIG_LIBATA
291#define CONFIG_SATA_ULI5288
292#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
293#define CONFIG_SYS_SCSI_MAX_LUN 1
294#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
295#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
296#endif
297
298#endif
299
300
301
302
303
304#define CONFIG_SYS_DBAT0L (BATL_PP_RW)
305#define CONFIG_SYS_IBAT0L (BATL_PP_RW)
306
307
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309
310
311
312
313
314#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
315 | BATL_GUARDEDSTORAGE)
316#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
317#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
318#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
319
320
321
322
323
324
325#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
326 | BATL_GUARDEDSTORAGE)
327#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
328#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
329#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
330
331
332
333
334
335
336#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
337 | BATL_GUARDEDSTORAGE)
338#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
339#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
340#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
341
342#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
343#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
344 | BATL_PP_RW | BATL_CACHEINHIBIT \
345 | BATL_GUARDEDSTORAGE)
346#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
347 | BATU_BL_1M | BATU_VS | BATU_VP)
348#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
349 | BATL_PP_RW | BATL_CACHEINHIBIT)
350#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
351#endif
352
353
354
355
356
357
358
359#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
360 | BATL_GUARDEDSTORAGE)
361#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
362#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
363#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
364
365
366
367
368
369#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
370#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
371#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
372#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
373
374
375
376
377
378#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
379 | BATL_GUARDEDSTORAGE)
380#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
381#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
382#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
383
384
385#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
386 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
387#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
388#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
389 | BATL_MEMCOHERENCE)
390#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
391
392
393
394
395
396#define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
397 | BATL_GUARDEDSTORAGE)
398#define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
399#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
400#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
401
402
403
404
405#ifndef CONFIG_SYS_RAMBOOT
406#define CONFIG_ENV_IS_IN_FLASH 1
407#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
408#define CONFIG_ENV_SECT_SIZE 0x20000
409#define CONFIG_ENV_SIZE 0x2000
410#else
411#define CONFIG_ENV_IS_NOWHERE 1
412#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
413#define CONFIG_ENV_SIZE 0x2000
414#endif
415
416#define CONFIG_LOADS_ECHO 1
417#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
418
419
420
421
422#define CONFIG_BOOTP_BOOTFILESIZE
423#define CONFIG_BOOTP_BOOTPATH
424#define CONFIG_BOOTP_GATEWAY
425#define CONFIG_BOOTP_HOSTNAME
426
427
428
429
430
431#if defined(CONFIG_PCI)
432#define CONFIG_CMD_PCI
433#define CONFIG_SCSI
434#endif
435
436#define CONFIG_WATCHDOG
437#define CONFIG_SYS_WATCHDOG_FREQ 5000
438
439
440
441
442#define CONFIG_SYS_LONGHELP
443#define CONFIG_CMDLINE_EDITING
444#define CONFIG_SYS_LOAD_ADDR 0x2000000
445
446#if defined(CONFIG_CMD_KGDB)
447#define CONFIG_SYS_CBSIZE 1024
448#else
449#define CONFIG_SYS_CBSIZE 256
450#endif
451
452#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
453#define CONFIG_SYS_MAXARGS 16
454#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
455
456
457
458
459
460
461#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
462#define CONFIG_SYS_BOOTM_LEN (256 << 20)
463
464#if defined(CONFIG_CMD_KGDB)
465#define CONFIG_KGDB_BAUDRATE 230400
466#endif
467
468
469
470
471#define CONFIG_IPADDR 192.168.1.100
472
473#define CONFIG_HOSTNAME unknown
474#define CONFIG_ROOTPATH "/opt/nfsroot"
475#define CONFIG_BOOTFILE "uImage"
476#define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
477
478#define CONFIG_SERVERIP 192.168.1.1
479#define CONFIG_GATEWAYIP 192.168.1.1
480#define CONFIG_NETMASK 255.255.255.0
481
482
483#define CONFIG_LOADADDR 0x10000000
484
485#undef CONFIG_BOOTARGS
486
487#if defined(CONFIG_PCI1)
488#define PCI_ENV \
489 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
490 "echo e;md ${a}e00 9\0" \
491 "pci1regs=setenv a e0008; run pcireg\0" \
492 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
493 "pci d.w $b.0 56 1\0" \
494 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
495 "pci w.w $b.0 56 ffff\0" \
496 "pci1err=setenv a e0008; run pcierr\0" \
497 "pci1errc=setenv a e0008; run pcierrc\0"
498#else
499#define PCI_ENV ""
500#endif
501
502#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
503#define PCIE_ENV \
504 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
505 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
506 "pcie1regs=setenv a e000a; run pciereg\0" \
507 "pcie2regs=setenv a e0009; run pciereg\0" \
508 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
509 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
510 "pci d $b.0 130 1\0" \
511 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
512 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
513 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
514 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
515 "pcie1err=setenv a e000a; run pcieerr\0" \
516 "pcie2err=setenv a e0009; run pcieerr\0" \
517 "pcie1errc=setenv a e000a; run pcieerrc\0" \
518 "pcie2errc=setenv a e0009; run pcieerrc\0"
519#else
520#define PCIE_ENV ""
521#endif
522
523#define DMA_ENV \
524 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
525 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
526 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
527 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
528 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
529 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
530 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
531 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
532
533#ifdef ENV_DEBUG
534#define CONFIG_EXTRA_ENV_SETTINGS \
535"netdev=eth0\0" \
536"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
537"tftpflash=tftpboot $loadaddr $uboot; " \
538 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
539 " +$filesize; " \
540 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
541 " +$filesize; " \
542 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
543 " $filesize; " \
544 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
545 " +$filesize; " \
546 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
547 " $filesize\0" \
548"consoledev=ttyS0\0" \
549"ramdiskaddr=0x18000000\0" \
550"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
551"fdtaddr=0x17c00000\0" \
552"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
553"bdev=sda3\0" \
554"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
555"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
556"maxcpus=1" \
557"eoi=mw e00400b0 0\0" \
558"iack=md e00400a0 1\0" \
559"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
560 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
561 "md ${a}f00 5\0" \
562"ddr1regs=setenv a e0002; run ddrreg\0" \
563"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
564 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
565 "md ${a}e60 1; md ${a}ef0 1d\0" \
566"guregs=setenv a e00e0; run gureg\0" \
567"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
568"mcmregs=setenv a e0001; run mcmreg\0" \
569"diuregs=md e002c000 1d\0" \
570"dium=mw e002c01c\0" \
571"diuerr=md e002c014 1\0" \
572"pmregs=md e00e1000 2b\0" \
573"lawregs=md e0000c08 4b\0" \
574"lbcregs=md e0005000 36\0" \
575"dma0regs=md e0021100 12\0" \
576"dma1regs=md e0021180 12\0" \
577"dma2regs=md e0021200 12\0" \
578"dma3regs=md e0021280 12\0" \
579 PCI_ENV \
580 PCIE_ENV \
581 DMA_ENV
582#else
583#define CONFIG_EXTRA_ENV_SETTINGS \
584 "netdev=eth0\0" \
585 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
586 "consoledev=ttyS0\0" \
587 "ramdiskaddr=0x18000000\0" \
588 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
589 "fdtaddr=0x17c00000\0" \
590 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
591 "bdev=sda3\0"
592#endif
593
594#define CONFIG_NFSBOOTCOMMAND \
595 "setenv bootargs root=/dev/nfs rw " \
596 "nfsroot=$serverip:$rootpath " \
597 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
598 "console=$consoledev,$baudrate $othbootargs;" \
599 "tftp $loadaddr $bootfile;" \
600 "tftp $fdtaddr $fdtfile;" \
601 "bootm $loadaddr - $fdtaddr"
602
603#define CONFIG_RAMBOOTCOMMAND \
604 "setenv bootargs root=/dev/ram rw " \
605 "console=$consoledev,$baudrate $othbootargs;" \
606 "tftp $ramdiskaddr $ramdiskfile;" \
607 "tftp $loadaddr $bootfile;" \
608 "tftp $fdtaddr $fdtfile;" \
609 "bootm $loadaddr $ramdiskaddr $fdtaddr"
610
611#define CONFIG_BOOTCOMMAND \
612 "setenv bootargs root=/dev/$bdev rw " \
613 "console=$consoledev,$baudrate $othbootargs;" \
614 "tftp $loadaddr $bootfile;" \
615 "tftp $fdtaddr $fdtfile;" \
616 "bootm $loadaddr - $fdtaddr"
617
618#endif
619