1
2
3
4
5
6
7
8
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#ifndef CONFIG_SYS_TEXT_BASE
14#define CONFIG_SYS_TEXT_BASE 0xeff40000
15#endif
16
17#ifndef CONFIG_SYS_MONITOR_BASE
18#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
19#endif
20
21#ifndef CONFIG_RESET_VECTOR_ADDRESS
22#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
23#endif
24
25
26#define CONFIG_MP
27
28#define CONFIG_PCI_INDIRECT_BRIDGE
29#define CONFIG_PCIE1
30#define CONFIG_PCIE2
31#define CONFIG_PCIE3
32#define CONFIG_FSL_PCI_INIT
33#define CONFIG_FSL_PCIE_RESET
34#define CONFIG_SYS_PCI_64BIT
35
36#ifndef __ASSEMBLY__
37extern unsigned long get_clock_freq(void);
38#endif
39
40#define CONFIG_SYS_CLK_FREQ 66666666
41#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
42
43
44
45
46#define CONFIG_L2_CACHE
47#define CONFIG_BTB
48#define CONFIG_HWCONFIG
49
50#define CONFIG_ENABLE_36BIT_PHYS
51
52#define CONFIG_SYS_MEMTEST_START 0x01000000
53#define CONFIG_SYS_MEMTEST_END 0x02000000
54
55#define CONFIG_PANIC_HANG
56
57
58#define CONFIG_SYS_LBC_LBCR 0x00000000
59#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
60
61
62#define CONFIG_VERY_BIG_RAM
63#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
64#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
65
66#define CONFIG_DIMM_SLOTS_PER_CTLR 1
67#define CONFIG_CHIP_SELECTS_PER_CTRL 1
68
69#define CONFIG_DDR_SPD
70#define CONFIG_FSL_DDR_INTERACTIVE
71#define CONFIG_SYS_SDRAM_SIZE 512u
72#define CONFIG_SYS_SPD_BUS_NUM 0
73#define SPD_EEPROM_ADDRESS 0x50
74#define CONFIG_SYS_DDR_RAW_TIMING
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96#define CONFIG_SYS_FLASH_BASE 0xec000000
97#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
98
99#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
100 | BR_PS_16 | BR_V)
101#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
102
103#define CONFIG_FLASH_CFI_DRIVER
104#define CONFIG_SYS_FLASH_CFI
105#define CONFIG_SYS_FLASH_EMPTY_INFO
106#define CONFIG_SYS_MAX_FLASH_BANKS 1
107#define CONFIG_SYS_MAX_FLASH_SECT 512
108#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
109#define CONFIG_SYS_FLASH_WRITE_TOUT 500
110
111#define CONFIG_BOARD_EARLY_INIT_R
112
113#define CONFIG_SYS_INIT_RAM_LOCK
114#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
115#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
116#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
117 GENERATED_GBL_DATA_SIZE)
118#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
119
120#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
121#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
122
123#define CONFIG_SYS_NAND_BASE 0xffa00000
124#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
125
126#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
127#define CONFIG_SYS_MAX_NAND_DEVICE 1
128#define CONFIG_CMD_NAND
129#define CONFIG_NAND_FSL_ELBC
130#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
131
132
133#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
134 | (2<<BR_DECC_SHIFT) \
135 | BR_PS_8 \
136 | BR_MS_FCM \
137 | BR_V)
138#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
139 | OR_FCM_PGS \
140 | OR_FCM_CSCT \
141 | OR_FCM_CST \
142 | OR_FCM_CHT \
143 | OR_FCM_SCY_1 \
144 | OR_FCM_TRLX \
145 | OR_FCM_EHTR)
146
147#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
148#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
149#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
150#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
151
152
153#define CONFIG_CONS_INDEX 1
154#undef CONFIG_SERIAL_SOFTWARE_FIFO
155#define CONFIG_SYS_NS16550_SERIAL
156#define CONFIG_SYS_NS16550_REG_SIZE 1
157#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
158
159#define CONFIG_SYS_BAUDRATE_TABLE \
160 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
161
162#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
163#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
164
165
166#define CONFIG_SYS_I2C
167#define CONFIG_SYS_I2C_FSL
168#define CONFIG_SYS_FSL_I2C_SPEED 400000
169#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
170#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
171#define CONFIG_SYS_FSL_I2C2_SPEED 400000
172#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
173#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
174
175
176
177
178#define CONFIG_ID_EEPROM
179#ifdef CONFIG_ID_EEPROM
180#define CONFIG_SYS_I2C_EEPROM_NXID
181#endif
182#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
183#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
184#define CONFIG_SYS_EEPROM_BUS_NUM 0
185
186
187
188
189
190
191
192#define CONFIG_SYS_PCIE3_NAME "Slot 3"
193#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
194#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
195#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
196#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
197#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
198#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
199#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
200#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
201
202
203#define CONFIG_SYS_PCIE2_NAME "Slot 2"
204#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
205#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
206#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
207#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
208#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
209#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
210#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
211#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
212
213
214#define CONFIG_SYS_PCIE1_NAME "Slot 1"
215#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
216#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
217#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
218#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
219#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
220#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
221#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
222#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
223
224#if defined(CONFIG_PCI)
225#define CONFIG_PCI_SCAN_SHOW
226#endif
227
228
229
230
231#define CONFIG_ENV_OVERWRITE
232
233#define CONFIG_ENV_IS_IN_FLASH
234#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
235#define CONFIG_ENV_SIZE 0x2000
236#define CONFIG_ENV_SECT_SIZE 0x20000
237
238#define CONFIG_LOADS_ECHO
239#define CONFIG_SYS_LOADS_BAUD_CHANGE
240
241
242
243
244#define CONFIG_CMD_REGINFO
245
246#if defined(CONFIG_PCI)
247#define CONFIG_CMD_PCI
248#endif
249
250
251
252
253#define CONFIG_HAS_FSL_DR_USB
254#ifdef CONFIG_HAS_FSL_DR_USB
255#ifdef CONFIG_USB_EHCI_HCD
256#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
257#define CONFIG_USB_EHCI_FSL
258#endif
259#endif
260
261
262
263
264#define CONFIG_SYS_LONGHELP
265#define CONFIG_CMDLINE_EDITING
266#define CONFIG_SYS_LOAD_ADDR 0x2000000
267#if defined(CONFIG_CMD_KGDB)
268#define CONFIG_SYS_CBSIZE 1024
269#else
270#define CONFIG_SYS_CBSIZE 256
271#endif
272
273#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
274#define CONFIG_SYS_MAXARGS 16
275
276#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
277
278
279
280
281
282
283#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
284#define CONFIG_SYS_BOOTM_LEN (64 << 20)
285
286
287
288
289#define CONFIG_BOOTFILE "uImage"
290#define CONFIG_UBOOTPATH (u-boot.bin)
291
292
293#define CONFIG_LOADADDR 1000000
294
295
296#define CONFIG_SYS_DPAA_QBMAN
297#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
298#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
299#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
300#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
301#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
302#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
303#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
304#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
305 CONFIG_SYS_QMAN_CENA_SIZE)
306#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
307#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
308#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
309#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
310#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
311#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
312#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
313#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
314#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
315#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
316 CONFIG_SYS_BMAN_CENA_SIZE)
317#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
318#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
319
320
321#define CONFIG_SYS_DPAA_FMAN
322#define CONFIG_PHY_GIGE
323
324#ifdef CONFIG_SYS_DPAA_FMAN
325#define CONFIG_FMAN_ENET
326#define CONFIG_PHY_ATHEROS
327#endif
328
329
330
331#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
332#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
333#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
334#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
335
336#ifdef CONFIG_FMAN_ENET
337#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
338#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
339
340#define CONFIG_SYS_TBIPA_VALUE 8
341#define CONFIG_MII
342#define CONFIG_ETHPRIME "FM1@DTSEC1"
343#endif
344
345#define CONFIG_EXTRA_ENV_SETTINGS \
346 "netdev=eth0\0" \
347 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
348 "loadaddr=1000000\0" \
349 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
350 "tftpflash=tftpboot $loadaddr $uboot; " \
351 "protect off $ubootaddr +$filesize; " \
352 "erase $ubootaddr +$filesize; " \
353 "cp.b $loadaddr $ubootaddr $filesize; " \
354 "protect on $ubootaddr +$filesize; " \
355 "cmp.b $loadaddr $ubootaddr $filesize\0" \
356 "consoledev=ttyS0\0" \
357 "ramdiskaddr=2000000\0" \
358 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
359 "fdtaddr=1e00000\0" \
360 "fdtfile=p1023rdb.dtb\0" \
361 "othbootargs=ramdisk_size=600000\0" \
362 "bdev=sda1\0" \
363 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
364
365#define CONFIG_HDBOOT \
366 "setenv bootargs root=/dev/$bdev rw " \
367 "console=$consoledev,$baudrate $othbootargs;" \
368 "tftp $loadaddr $bootfile;" \
369 "tftp $fdtaddr $fdtfile;" \
370 "bootm $loadaddr - $fdtaddr"
371
372#define CONFIG_NFSBOOTCOMMAND \
373 "setenv bootargs root=/dev/nfs rw " \
374 "nfsroot=$serverip:$rootpath " \
375 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
376 "console=$consoledev,$baudrate $othbootargs;" \
377 "tftp $loadaddr $bootfile;" \
378 "tftp $fdtaddr $fdtfile;" \
379 "bootm $loadaddr - $fdtaddr"
380
381#define CONFIG_RAMBOOTCOMMAND \
382 "setenv bootargs root=/dev/ram rw " \
383 "console=$consoledev,$baudrate $othbootargs;" \
384 "tftp $ramdiskaddr $ramdiskfile;" \
385 "tftp $loadaddr $bootfile;" \
386 "tftp $fdtaddr $fdtfile;" \
387 "bootm $loadaddr $ramdiskaddr $fdtaddr"
388
389#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
390
391#endif
392