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6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10#define CONFIG_CYRUS
11
12#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
13#error Must call Cyrus CONFIG with a specific CPU enabled.
14#endif
15
16#define CONFIG_SDCARD
17#define CONFIG_FSL_SATA_V2
18#define CONFIG_PCIE3
19#define CONFIG_PCIE4
20#ifdef CONFIG_ARCH_P5020
21#define CONFIG_SYS_FSL_RAID_ENGINE
22#define CONFIG_SYS_DPAA_RMAN
23#endif
24#define CONFIG_SYS_DPAA_PME
25
26
27
28
29#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
30#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
31#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
32#if defined(CONFIG_ARCH_P5020)
33#define CONFIG_SYS_CLK_FREQ 133000000
34#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
35#elif defined(CONFIG_ARCH_P5040)
36#define CONFIG_SYS_CLK_FREQ 100000000
37#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
38#endif
39
40
41#define CONFIG_SYS_BOOK3E_HV
42#define CONFIG_MP
43
44#define CONFIG_SYS_MMC_MAX_DEVICE 1
45
46#ifndef CONFIG_SYS_TEXT_BASE
47#define CONFIG_SYS_TEXT_BASE 0xeff40000
48#endif
49
50#define CONFIG_SYS_FSL_CPC
51#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
52#define CONFIG_PCIE1
53#define CONFIG_PCIE2
54#define CONFIG_FSL_PCI_INIT
55#define CONFIG_SYS_PCI_64BIT
56
57#define CONFIG_ENV_OVERWRITE
58
59#if defined(CONFIG_SDCARD)
60#define CONFIG_SYS_EXTRA_ENV_RELOC
61#define CONFIG_ENV_IS_IN_MMC
62#define CONFIG_FSL_FIXED_MMC_LOCATION
63#define CONFIG_SYS_MMC_ENV_DEV 0
64#define CONFIG_ENV_SIZE 0x2000
65#define CONFIG_ENV_OFFSET (512 * 1658)
66#endif
67
68
69
70
71#define CONFIG_SYS_CACHE_STASHING
72#define CONFIG_BACKSIDE_L2_CACHE
73#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
74#define CONFIG_BTB
75#define CONFIG_DDR_ECC
76#ifdef CONFIG_DDR_ECC
77#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
78#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
79#endif
80
81#define CONFIG_ENABLE_36BIT_PHYS
82
83#ifdef CONFIG_PHYS_64BIT
84#define CONFIG_ADDR_MAP
85#define CONFIG_SYS_NUM_ADDR_MAP 64
86#endif
87
88
89#undef CONFIG_POST
90#define CONFIG_SYS_MEMTEST_START 0x00200000
91#define CONFIG_SYS_MEMTEST_END 0x00400000
92#define CONFIG_SYS_ALT_MEMTEST
93#define CONFIG_PANIC_HANG
94
95
96
97
98#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
99#ifdef CONFIG_PHYS_64BIT
100#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
101#else
102#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
103#endif
104#define CONFIG_SYS_L3_SIZE (1024 << 10)
105#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
106
107#ifdef CONFIG_PHYS_64BIT
108#define CONFIG_SYS_DCSRBAR 0xf0000000
109#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
110#endif
111
112
113
114
115#define CONFIG_VERY_BIG_RAM
116#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
117#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
118
119#define CONFIG_DIMM_SLOTS_PER_CTLR 1
120#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
121
122#define CONFIG_DDR_SPD
123
124#define CONFIG_SYS_SPD_BUS_NUM 1
125#define SPD_EEPROM_ADDRESS1 0x51
126#define SPD_EEPROM_ADDRESS2 0x52
127#define CONFIG_SYS_SDRAM_SIZE 4096
128
129
130
131
132
133#define CONFIG_SYS_LBC0_BASE 0xe0000000
134#ifdef CONFIG_PHYS_64BIT
135#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
136#else
137#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
138#endif
139
140#define CONFIG_SYS_LBC1_BASE 0xe1000000
141#ifdef CONFIG_PHYS_64BIT
142#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
143#else
144#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
145#endif
146
147
148#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1)
149
150#define CONFIG_SYS_BR0_PRELIM \
151(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
152#define CONFIG_SYS_BR1_PRELIM \
153(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
154
155#define CONFIG_SYS_OR0_PRELIM 0xfff00010
156#define CONFIG_SYS_OR1_PRELIM 0xfff00010
157
158#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
159
160#if defined(CONFIG_RAMBOOT_PBL)
161#define CONFIG_SYS_RAMBOOT
162#endif
163
164#define CONFIG_BOARD_EARLY_INIT_R
165#define CONFIG_MISC_INIT_R
166
167#define CONFIG_HWCONFIG
168
169
170#define CONFIG_L1_INIT_RAM
171#define CONFIG_SYS_INIT_RAM_LOCK
172#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
173#ifdef CONFIG_PHYS_64BIT
174#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
175#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
176
177#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
178 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
179 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
180#else
181#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
182#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
183#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
184#endif
185#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
186
187#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
188#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
189
190#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
191#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
192
193
194
195
196
197#define CONFIG_CONS_INDEX 1
198#define CONFIG_SYS_NS16550_SERIAL
199#define CONFIG_SYS_NS16550_REG_SIZE 1
200#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
201
202#define CONFIG_SYS_BAUDRATE_TABLE \
203{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
204
205#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
206#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
207#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
208#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
209
210
211#define CONFIG_SYS_I2C
212#define CONFIG_SYS_I2C_FSL
213#define CONFIG_I2C_MULTI_BUS
214#define CONFIG_I2C_CMD_TREE
215#define CONFIG_SYS_FSL_I2C_SPEED 400000
216#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
217#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
218#define CONFIG_SYS_FSL_I2C2_SPEED 400000
219#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
220#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
221#define CONFIG_SYS_FSL_I2C3_SPEED 400000
222#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
223#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
224#define CONFIG_SYS_FSL_I2C4_SPEED 400000
225#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
226#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
227
228#define CONFIG_ID_EEPROM
229#define CONFIG_SYS_I2C_EEPROM_NXID
230#define CONFIG_SYS_EEPROM_BUS_NUM 0
231#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
232#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
233
234#define CONFIG_SYS_I2C_GENERIC_MAC
235#define CONFIG_SYS_I2C_MAC1_BUS 3
236#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
237#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
238#define CONFIG_SYS_I2C_MAC2_BUS 0
239#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
240#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
241
242#define CONFIG_RTC_MCP79411 1
243#define CONFIG_SYS_RTC_BUS_NUM 3
244#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
245
246
247
248
249
250
251
252
253
254
255
256#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
257#ifdef CONFIG_PHYS_64BIT
258#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
259#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
260#else
261#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
262#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
263#endif
264#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
265#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
266#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
267#ifdef CONFIG_PHYS_64BIT
268#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
269#else
270#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
271#endif
272#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
273
274
275#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
276#ifdef CONFIG_PHYS_64BIT
277#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
278#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
279#else
280#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
281#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
282#endif
283#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
284#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
285#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
286#ifdef CONFIG_PHYS_64BIT
287#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
288#else
289#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
290#endif
291#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
292
293
294#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
295#ifdef CONFIG_PHYS_64BIT
296#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
297#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
298#else
299#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
300#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
301#endif
302#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
303#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
304#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
305#ifdef CONFIG_PHYS_64BIT
306#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
307#else
308#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
309#endif
310#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
311
312
313#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
314#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
315#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000
316#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
317#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
318#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
319
320
321#define CONFIG_SYS_DPAA_QBMAN
322#define CONFIG_SYS_BMAN_NUM_PORTALS 10
323#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
324#ifdef CONFIG_PHYS_64BIT
325#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
326#else
327#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
328#endif
329#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
330#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
331#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
332#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
333#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
334#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
335 CONFIG_SYS_BMAN_CENA_SIZE)
336#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
337#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
338#define CONFIG_SYS_QMAN_NUM_PORTALS 10
339#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
340#ifdef CONFIG_PHYS_64BIT
341#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
342#else
343#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
344#endif
345#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
346#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
347#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
348#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
349#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
350#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
351 CONFIG_SYS_QMAN_CENA_SIZE)
352#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
353#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
354
355#define CONFIG_SYS_DPAA_FMAN
356
357
358
359
360
361
362#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
363#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
364
365#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
366#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
367
368#ifdef CONFIG_SYS_DPAA_FMAN
369#define CONFIG_FMAN_ENET
370#define CONFIG_PHY_MICREL
371#define CONFIG_PHY_MICREL_KSZ9021
372#endif
373
374#ifdef CONFIG_PCI
375#define CONFIG_PCI_INDIRECT_BRIDGE
376#define CONFIG_NET_MULTI
377
378#define CONFIG_PCI_SCAN_SHOW
379#endif
380
381
382#ifdef CONFIG_FSL_SATA_V2
383#define CONFIG_LIBATA
384#define CONFIG_FSL_SATA
385
386#define CONFIG_SYS_SATA_MAX_DEVICE 2
387#define CONFIG_SATA1
388#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
389#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
390#define CONFIG_SATA2
391#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
392#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
393
394#define CONFIG_LBA48
395#define CONFIG_CMD_SATA
396#endif
397
398#ifdef CONFIG_FMAN_ENET
399#define CONFIG_SYS_TBIPA_VALUE 8
400#define CONFIG_MII
401#define CONFIG_ETHPRIME "FM1@DTSEC4"
402#define CONFIG_PHY_GIGE
403#endif
404
405
406
407
408#define CONFIG_LOADS_ECHO
409#define CONFIG_SYS_LOADS_BAUD_CHANGE
410
411
412
413
414#define CONFIG_CMD_REGINFO
415
416#ifdef CONFIG_PCI
417#define CONFIG_CMD_PCI
418#endif
419
420
421
422
423#define CONFIG_HAS_FSL_DR_USB
424#define CONFIG_HAS_FSL_MPH_USB
425
426#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
427#define CONFIG_USB_EHCI_FSL
428#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
429#define CONFIG_EHCI_IS_TDI
430#define CONFIG_SYS_USB_EVENT_POLL
431
432#endif
433
434#ifdef CONFIG_MMC
435#define CONFIG_FSL_ESDHC
436#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
437#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
438#endif
439
440
441
442
443#define CONFIG_SYS_LONGHELP
444#define CONFIG_CMDLINE_EDITING
445#define CONFIG_AUTO_COMPLETE
446#define CONFIG_SYS_LOAD_ADDR 0x2000000
447#ifdef CONFIG_CMD_KGDB
448#define CONFIG_SYS_CBSIZE 1024
449#else
450#define CONFIG_SYS_CBSIZE 256
451#endif
452#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
453#define CONFIG_SYS_MAXARGS 16
454#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
455
456
457
458
459
460
461#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
462#define CONFIG_SYS_BOOTM_LEN (64 << 20)
463
464#ifdef CONFIG_CMD_KGDB
465#define CONFIG_KGDB_BAUDRATE 230400
466#endif
467
468
469
470
471#define CONFIG_ROOTPATH "/opt/nfsroot"
472#define CONFIG_BOOTFILE "uImage"
473#define CONFIG_UBOOTPATH u-boot.bin
474
475
476#define CONFIG_LOADADDR 1000000
477
478#define __USB_PHY_TYPE utmi
479
480#define CONFIG_EXTRA_ENV_SETTINGS \
481"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
482"bank_intlv=cs0_cs1;" \
483"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
484"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
485"netdev=eth0\0" \
486"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
487"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
488"consoledev=ttyS0\0" \
489"ramdiskaddr=2000000\0" \
490"fdtaddr=1e00000\0" \
491"bdev=sda3\0"
492
493#define CONFIG_HDBOOT \
494"setenv bootargs root=/dev/$bdev rw " \
495"console=$consoledev,$baudrate $othbootargs;" \
496"tftp $loadaddr $bootfile;" \
497"tftp $fdtaddr $fdtfile;" \
498"bootm $loadaddr - $fdtaddr"
499
500#define CONFIG_NFSBOOTCOMMAND \
501"setenv bootargs root=/dev/nfs rw " \
502"nfsroot=$serverip:$rootpath " \
503"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
504"console=$consoledev,$baudrate $othbootargs;" \
505"tftp $loadaddr $bootfile;" \
506"tftp $fdtaddr $fdtfile;" \
507"bootm $loadaddr - $fdtaddr"
508
509#define CONFIG_RAMBOOTCOMMAND \
510"setenv bootargs root=/dev/ram rw " \
511"console=$consoledev,$baudrate $othbootargs;" \
512"tftp $ramdiskaddr $ramdiskfile;" \
513"tftp $loadaddr $bootfile;" \
514"tftp $fdtaddr $fdtfile;" \
515"bootm $loadaddr $ramdiskaddr $fdtaddr"
516
517#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
518
519#include <asm/fsl_secure_boot.h>
520
521#ifdef CONFIG_SECURE_BOOT
522#endif
523
524#endif
525