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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include <asm/hardware.h>
14
15
16#define CONFIG_SYS_TEXT_BASE 0x27000000
17
18
19#define CONFIG_SKIP_LOWLEVEL_INIT
20
21
22#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
23
24
25#define CONFIG_ARCH_CPU_INIT
26
27
28#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
29#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
30
31
32#define CONFIG_SRAM_BASE 0x00300000
33#define CONFIG_SRAM_SIZE (32 << 10)
34#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
35 GENERATED_GBL_DATA_SIZE)
36
37
38#define CONFIG_NR_DRAM_BANKS 1
39#define CONFIG_SYS_SDRAM_BASE 0x20000000
40#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
41#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
42#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
43#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
44#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
45#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
46 - CONFIG_SYS_MALLOC_LEN)
47
48
49# define CONFIG_SYS_MAX_FLASH_BANKS 1
50# define CONFIG_SYS_FLASH_BASE 0x00200000
51# define CONFIG_AT91_EFLASH
52# define CONFIG_SYS_MAX_FLASH_SECT 32
53# define CONFIG_SYS_FLASH_PROTECTION
54# define CONFIG_EFLASH_PROTSECTORS 1
55
56
57#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
58#define CONFIG_HAS_DATAFLASH
59#define CONFIG_ATMEL_DATAFLASH_SPI
60#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
61#define DATAFLASH_TCSS (0x1a << 16)
62#define DATAFLASH_TCHS (0x1 << 24)
63
64#define CONFIG_ENV_IS_IN_SPI_FLASH
65#define CONFIG_ENV_OFFSET 0x3DE000
66#define CONFIG_ENV_SECT_SIZE (132 << 10)
67#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
68#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
69 + CONFIG_ENV_OFFSET)
70#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
71 + 0x042000)
72
73
74#define CONFIG_ATMEL_SPI
75#define AT91_SPI_CLK 15000000
76
77
78#define CONFIG_ATMEL_USART
79#define CONFIG_USART3
80#define CONFIG_USART_BASE ATMEL_BASE_DBGU
81#define CONFIG_USART_ID ATMEL_ID_SYS
82
83
84#define CONFIG_AT91_GPIO
85
86
87#define CONFIG_CMD_MTDPARTS
88#define CONFIG_CMD_NAND
89
90#ifndef MINIMAL_LOADER
91#define CONFIG_CMD_REISER
92#define CONFIG_CMD_SAVES
93#define CONFIG_CMD_UBIFS
94#endif
95
96
97#ifdef CONFIG_CMD_NAND
98#define CONFIG_SYS_MAX_NAND_DEVICE 1
99#define CONFIG_SYS_NAND_BASE 0x40000000
100#define CONFIG_SYS_NAND_DBW_8
101#define CONFIG_NAND_ATMEL
102
103#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
104
105#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
106#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
107#endif
108
109
110#ifdef CONFIG_CMD_JFFS2
111#define CONFIG_JFFS2_CMDLINE
112#define CONFIG_JFFS2_NAND
113#endif
114
115
116#define CONFIG_NET_RETRY_COUNT 20
117#define CONFIG_MACB
118#define CONFIG_RMII
119#define CONFIG_PHY_ID 0
120#define CONFIG_MACB_SEARCH_PHY
121
122
123#ifdef CONFIG_CMD_MMC
124#define CONFIG_GENERIC_ATMEL_MCI
125#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
126#endif
127
128
129#ifdef CONFIG_CMD_USB
130#define CONFIG_USB_ATMEL
131#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
132#define CONFIG_USB_OHCI_NEW
133#define CONFIG_SYS_USB_OHCI_CPU_INIT
134#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
135#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
136#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
137#endif
138
139
140#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
141#define CONFIG_RTC_PCF8563
142#define CONFIG_SYS_I2C_RTC_ADDR 0x51
143#endif
144
145
146#define CONFIG_SYS_MAX_I2C_BUS 1
147
148#define CONFIG_SYS_I2C
149#define CONFIG_SYS_I2C_SOFT
150#define CONFIG_SYS_I2C_SOFT_SPEED 100000
151#define CONFIG_SYS_I2C_SOFT_SLAVE 0
152
153#define I2C_SOFT_DECLARATIONS
154
155#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
156#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
157
158#define I2C_INIT { \
159 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
160 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
161 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
162 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
163 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
164}
165
166#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
167#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
168#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
169#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
170#define I2C_DELAY udelay(100)
171#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
172
173
174#ifdef CONFIG_CMD_DHCP
175#define CONFIG_BOOTP_BOOTFILESIZE
176#define CONFIG_BOOTP_BOOTPATH
177#define CONFIG_BOOTP_GATEWAY
178#define CONFIG_BOOTP_HOSTNAME
179#define CONFIG_SYS_AUTOLOAD "n"
180#endif
181
182
183#define CONFIG_MTD_DEVICE
184#define CONFIG_MTD_PARTITIONS
185#if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
186#define MTDIDS_DEFAULT "nand0=atmel_nand"
187#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)"
188#endif
189#define CONFIG_LZO
190#define CONFIG_RBTREE
191
192
193#define CONFIG_CMDLINE_TAG
194#define CONFIG_SETUP_MEMORY_TAGS
195#define CONFIG_INITRD_TAG
196#define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
197#if defined(CONFIG_CMD_NAND)
198#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
199 "root=/dev/mtdblock0 " \
200 MTDPARTS_DEFAULT \
201 " rw rootfstype=jffs2"
202#endif
203
204
205#define CONFIG_SYS_CBSIZE 256
206#define CONFIG_SYS_MAXARGS 16
207#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \
208 + sizeof(CONFIG_SYS_PROMPT))
209#define CONFIG_SYS_LONGHELP
210#define CONFIG_CMDLINE_EDITING
211
212#endif
213