1/* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the Freescale i.MX6Q SabreAuto board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __MX6QSABREAUTO_CONFIG_H 10#define __MX6QSABREAUTO_CONFIG_H 11 12#define CONFIG_MACH_TYPE 3529 13#define CONFIG_MXC_UART_BASE UART4_BASE 14#define CONSOLE_DEV "ttymxc3" 15#define CONFIG_MMCROOT "/dev/mmcblk0p2" 16 17/* USB Configs */ 18#define CONFIG_USB_HOST_ETHER 19#define CONFIG_USB_ETHER_ASIX 20#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 21#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 22#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 23#define CONFIG_MXC_USB_FLAGS 0 24 25#define CONFIG_PCA953X 26#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } 27 28#include "mx6sabre_common.h" 29 30#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR 31#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) 32#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 33#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 34#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ 35#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ 36#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ 37#define CONFIG_SYS_FLASH_EMPTY_INFO 38#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 39 40#define CONFIG_SYS_FSL_USDHC_NUM 2 41#if defined(CONFIG_ENV_IS_IN_MMC) 42#define CONFIG_SYS_MMC_ENV_DEV 0 43#endif 44 45/* I2C Configs */ 46#define CONFIG_SYS_I2C 47#define CONFIG_SYS_I2C_MXC 48#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 49#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 50#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 51#define CONFIG_SYS_I2C_SPEED 100000 52 53/* NAND flash command */ 54#define CONFIG_CMD_NAND 55#define CONFIG_CMD_NAND_TRIMFFS 56 57/* NAND stuff */ 58#define CONFIG_NAND_MXS 59#define CONFIG_SYS_MAX_NAND_DEVICE 1 60#define CONFIG_SYS_NAND_BASE 0x40000000 61#define CONFIG_SYS_NAND_5_ADDR_CYCLE 62#define CONFIG_SYS_NAND_ONFI_DETECTION 63 64/* DMA stuff, needed for GPMI/MXS NAND support */ 65#define CONFIG_APBH_DMA 66#define CONFIG_APBH_DMA_BURST 67#define CONFIG_APBH_DMA_BURST8 68 69/* PMIC */ 70#define CONFIG_POWER 71#define CONFIG_POWER_I2C 72#define CONFIG_POWER_PFUZE100 73#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 74 75#endif /* __MX6QSABREAUTO_CONFIG_H */ 76