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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#if defined(CONFIG_TWR_P1025)
14#define CONFIG_BOARDNAME "TWR-P1025"
15#define CONFIG_PHY_ATHEROS
16#define CONFIG_QE
17#define CONFIG_SYS_LBC_LBCR 0x00080000
18#define CONFIG_SYS_LBC_LCRR 0x80000002
19#endif
20
21#ifdef CONFIG_SDCARD
22#define CONFIG_RAMBOOT_SDCARD
23#define CONFIG_SYS_RAMBOOT
24#define CONFIG_SYS_EXTRA_ENV_RELOC
25#define CONFIG_SYS_TEXT_BASE 0x11000000
26#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
27#endif
28
29#ifndef CONFIG_SYS_TEXT_BASE
30#define CONFIG_SYS_TEXT_BASE 0xeff40000
31#endif
32
33#ifndef CONFIG_RESET_VECTOR_ADDRESS
34#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
35#endif
36
37#ifndef CONFIG_SYS_MONITOR_BASE
38#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
39#endif
40
41#define CONFIG_MP
42
43#define CONFIG_PCIE1
44#define CONFIG_PCIE2
45#define CONFIG_FSL_PCI_INIT
46#define CONFIG_PCI_INDIRECT_BRIDGE
47#define CONFIG_FSL_PCIE_RESET
48#define CONFIG_SYS_PCI_64BIT
49
50#define CONFIG_TSEC_ENET
51#define CONFIG_ENV_OVERWRITE
52
53#define CONFIG_CMD_SATA
54#define CONFIG_SATA_SIL3114
55#define CONFIG_SYS_SATA_MAX_DEVICE 2
56#define CONFIG_LIBATA
57#define CONFIG_LBA48
58
59#ifndef __ASSEMBLY__
60extern unsigned long get_board_sys_clk(unsigned long dummy);
61#endif
62#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
63
64#define CONFIG_DDR_CLK_FREQ 66666666
65
66#define CONFIG_HWCONFIG
67
68
69
70#define CONFIG_L2_CACHE
71#define CONFIG_BTB
72
73#define CONFIG_SYS_MEMTEST_START 0x00200000
74#define CONFIG_SYS_MEMTEST_END 0x1fffffff
75#define CONFIG_PANIC_HANG
76
77#define CONFIG_SYS_CCSRBAR 0xffe00000
78#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
79
80
81
82#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
83#define CONFIG_CHIP_SELECTS_PER_CTRL 1
84
85#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
86#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
87#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
88
89#define CONFIG_DIMM_SLOTS_PER_CTLR 1
90
91
92#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
93#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
94#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
95#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
96#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
97#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
98
99#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
100#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
101#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
102#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
103
104#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
105#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
106#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
107#define CONFIG_SYS_DDR_RCW_1 0x00000000
108#define CONFIG_SYS_DDR_RCW_2 0x00000000
109#define CONFIG_SYS_DDR_CONTROL 0xc70c0000
110#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
111#define CONFIG_SYS_DDR_TIMING_4 0x00220001
112#define CONFIG_SYS_DDR_TIMING_5 0x03402400
113
114#define CONFIG_SYS_DDR_TIMING_3 0x00020000
115#define CONFIG_SYS_DDR_TIMING_0 0x00220004
116#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
117#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
118#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
119#define CONFIG_SYS_DDR_MODE_1 0x80461320
120#define CONFIG_SYS_DDR_MODE_2 0x00008000
121#define CONFIG_SYS_DDR_INTERVAL 0x09480000
122
123
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126
127
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139
140
141
142#define CONFIG_SYS_MAX_FLASH_SECT 512
143#define CONFIG_SYS_FLASH_BASE 0xec000000
144
145#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
146
147#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
148 | BR_PS_16 | BR_V)
149
150#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
151
152#define CONFIG_SYS_SSD_BASE 0xe0000000
153#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
154#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
155 BR_PS_16 | BR_V)
156#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
157 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
158 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
159
160#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
161#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
162
163#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
164#define CONFIG_SYS_FLASH_QUIET_TEST
165#define CONFIG_FLASH_SHOW_PROGRESS 45
166
167#define CONFIG_SYS_MAX_FLASH_BANKS 1
168
169#undef CONFIG_SYS_FLASH_CHECKSUM
170#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
171#define CONFIG_SYS_FLASH_WRITE_TOUT 500
172
173#define CONFIG_FLASH_CFI_DRIVER
174#define CONFIG_SYS_FLASH_CFI
175#define CONFIG_SYS_FLASH_EMPTY_INFO
176#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
177
178#define CONFIG_BOARD_EARLY_INIT_R
179
180#define CONFIG_SYS_INIT_RAM_LOCK
181#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
182
183#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
184#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
185#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
186
187#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
188
189#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
190 GENERATED_GBL_DATA_SIZE)
191#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
192
193#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
194#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
195
196#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
197#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
198
199
200
201
202
203#define CONFIG_CONS_INDEX 1
204#undef CONFIG_SERIAL_SOFTWARE_FIFO
205#define CONFIG_SYS_NS16550_SERIAL
206#define CONFIG_SYS_NS16550_REG_SIZE 1
207#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
208
209#define CONFIG_SYS_BAUDRATE_TABLE \
210 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
211
212#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
213#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
214
215
216#define CONFIG_SYS_I2C
217#define CONFIG_SYS_I2C_FSL
218#define CONFIG_SYS_FSL_I2C_SPEED 400000
219#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
220#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
221#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
222
223
224
225
226#define CONFIG_SYS_FSL_I2C2_SPEED 400000
227#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
228#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
229
230#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
231
232
233#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
234#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
235#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
236
237
238
239
240#define CONFIG_HARD_SPI
241
242#if defined(CONFIG_PCI)
243
244
245
246
247
248
249#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
250#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
251#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
252#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
253#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
254#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
255#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
256#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
257#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
258
259
260#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
261#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
262#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
263#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
264#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
265#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
266#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
267#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
268#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
269
270#define CONFIG_CMD_PCI
271
272#define CONFIG_PCI_SCAN_SHOW
273#endif
274
275#if defined(CONFIG_TSEC_ENET)
276
277#define CONFIG_MII
278#define CONFIG_TSEC1
279#define CONFIG_TSEC1_NAME "eTSEC1"
280#undef CONFIG_TSEC2
281#undef CONFIG_TSEC2_NAME
282#define CONFIG_TSEC3
283#define CONFIG_TSEC3_NAME "eTSEC3"
284
285#define TSEC1_PHY_ADDR 2
286#define TSEC2_PHY_ADDR 0
287#define TSEC3_PHY_ADDR 1
288
289#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
290#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
291#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
292
293#define TSEC1_PHYIDX 0
294#define TSEC2_PHYIDX 0
295#define TSEC3_PHYIDX 0
296
297#define CONFIG_ETHPRIME "eTSEC1"
298
299#define CONFIG_PHY_GIGE 1
300
301#define CONFIG_HAS_ETH0
302#define CONFIG_HAS_ETH1
303#undef CONFIG_HAS_ETH2
304#endif
305
306#ifdef CONFIG_QE
307
308#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
309#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
310#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
311#endif
312
313#ifdef CONFIG_TWR_P1025
314
315
316
317#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
318
319#undef CONFIG_UEC_ETH
320#define CONFIG_PHY_MODE_NEED_CHANGE
321
322#define CONFIG_UEC_ETH1
323#define CONFIG_HAS_ETH0
324
325#ifdef CONFIG_UEC_ETH1
326#define CONFIG_SYS_UEC1_UCC_NUM 0
327#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12
328#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
329#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
330#define CONFIG_SYS_UEC1_PHY_ADDR 0x18
331#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
332#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
333#endif
334
335#define CONFIG_UEC_ETH5
336#define CONFIG_HAS_ETH1
337
338#ifdef CONFIG_UEC_ETH5
339#define CONFIG_SYS_UEC5_UCC_NUM 4
340#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
341#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13
342#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
343#define CONFIG_SYS_UEC5_PHY_ADDR 0x19
344#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
345#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
346#endif
347#endif
348
349
350
351
352#define CONFIG_MTD_DEVICE
353#define CONFIG_MTD_PARTITIONS
354#define CONFIG_CMD_MTDPARTS
355#define CONFIG_FLASH_CFI_MTD
356#define MTDIDS_DEFAULT "nor0=ec000000.nor"
357#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
358 "256k(dtb),5632k(kernel),57856k(fs)," \
359 "256k(qe-ucode-firmware),1280k(u-boot)"
360
361
362
363
364#ifdef CONFIG_SYS_RAMBOOT
365#ifdef CONFIG_RAMBOOT_SDCARD
366#define CONFIG_ENV_IS_IN_MMC
367#define CONFIG_ENV_SIZE 0x2000
368#define CONFIG_SYS_MMC_ENV_DEV 0
369#else
370#define CONFIG_ENV_IS_NOWHERE
371#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
372#define CONFIG_ENV_SIZE 0x2000
373#endif
374#else
375#define CONFIG_ENV_IS_IN_FLASH
376#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
377#define CONFIG_ENV_SIZE 0x2000
378#define CONFIG_ENV_SECT_SIZE 0x20000
379#endif
380
381#define CONFIG_LOADS_ECHO
382#define CONFIG_SYS_LOADS_BAUD_CHANGE
383
384
385
386
387#define CONFIG_CMD_REGINFO
388
389
390
391
392#define CONFIG_HAS_FSL_DR_USB
393
394#if defined(CONFIG_HAS_FSL_DR_USB)
395#ifdef CONFIG_USB_EHCI_HCD
396#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
397#define CONFIG_USB_EHCI_FSL
398#endif
399#endif
400
401#ifdef CONFIG_MMC
402#define CONFIG_FSL_ESDHC
403#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
404#endif
405
406#undef CONFIG_WATCHDOG
407
408
409
410
411#define CONFIG_SYS_LONGHELP
412#define CONFIG_CMDLINE_EDITING
413#define CONFIG_SYS_LOAD_ADDR 0x2000000
414#if defined(CONFIG_CMD_KGDB)
415#define CONFIG_SYS_CBSIZE 1024
416#else
417#define CONFIG_SYS_CBSIZE 256
418#endif
419#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
420
421#define CONFIG_SYS_MAXARGS 16
422#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
423
424
425
426
427
428
429#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
430#define CONFIG_SYS_BOOTM_LEN (64 << 20)
431
432
433
434
435#define CONFIG_HOSTNAME unknown
436#define CONFIG_ROOTPATH "/opt/nfsroot"
437#define CONFIG_BOOTFILE "uImage"
438#define CONFIG_UBOOTPATH u-boot.bin
439
440
441#define CONFIG_LOADADDR 1000000
442
443#define CONFIG_BOOTARGS
444
445#define CONFIG_EXTRA_ENV_SETTINGS \
446"netdev=eth0\0" \
447"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
448"loadaddr=1000000\0" \
449"bootfile=uImage\0" \
450"dtbfile=twr-p1025twr.dtb\0" \
451"ramdiskfile=rootfs.ext2.gz.uboot\0" \
452"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
453"tftpflash=tftpboot $loadaddr $uboot; " \
454 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
455 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
456 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
457 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
458 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
459"kernelflash=tftpboot $loadaddr $bootfile; " \
460 "protect off 0xefa80000 +$filesize; " \
461 "erase 0xefa80000 +$filesize; " \
462 "cp.b $loadaddr 0xefa80000 $filesize; " \
463 "protect on 0xefa80000 +$filesize; " \
464 "cmp.b $loadaddr 0xefa80000 $filesize\0" \
465"dtbflash=tftpboot $loadaddr $dtbfile; " \
466 "protect off 0xefe80000 +$filesize; " \
467 "erase 0xefe80000 +$filesize; " \
468 "cp.b $loadaddr 0xefe80000 $filesize; " \
469 "protect on 0xefe80000 +$filesize; " \
470 "cmp.b $loadaddr 0xefe80000 $filesize\0" \
471"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
472 "protect off 0xeeb80000 +$filesize; " \
473 "erase 0xeeb80000 +$filesize; " \
474 "cp.b $loadaddr 0xeeb80000 $filesize; " \
475 "protect on 0xeeb80000 +$filesize; " \
476 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \
477"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
478 "protect off 0xefec0000 +$filesize; " \
479 "erase 0xefec0000 +$filesize; " \
480 "cp.b $loadaddr 0xefec0000 $filesize; " \
481 "protect on 0xefec0000 +$filesize; " \
482 "cmp.b $loadaddr 0xefec0000 $filesize\0" \
483"consoledev=ttyS0\0" \
484"ramdiskaddr=2000000\0" \
485"ramdiskfile=rootfs.ext2.gz.uboot\0" \
486"fdtaddr=1e00000\0" \
487"bdev=sda1\0" \
488"norbootaddr=ef080000\0" \
489"norfdtaddr=ef040000\0" \
490"ramdisk_size=120000\0" \
491"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
492"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
493
494#define CONFIG_NFSBOOTCOMMAND \
495"setenv bootargs root=/dev/nfs rw " \
496"nfsroot=$serverip:$rootpath " \
497"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
498"console=$consoledev,$baudrate $othbootargs;" \
499"tftp $loadaddr $bootfile&&" \
500"tftp $fdtaddr $fdtfile&&" \
501"bootm $loadaddr - $fdtaddr"
502
503#define CONFIG_HDBOOT \
504"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
505"console=$consoledev,$baudrate $othbootargs;" \
506"usb start;" \
507"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
508"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
509"bootm $loadaddr - $fdtaddr"
510
511#define CONFIG_USB_FAT_BOOT \
512"setenv bootargs root=/dev/ram rw " \
513"console=$consoledev,$baudrate $othbootargs " \
514"ramdisk_size=$ramdisk_size;" \
515"usb start;" \
516"fatload usb 0:2 $loadaddr $bootfile;" \
517"fatload usb 0:2 $fdtaddr $fdtfile;" \
518"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
519"bootm $loadaddr $ramdiskaddr $fdtaddr"
520
521#define CONFIG_USB_EXT2_BOOT \
522"setenv bootargs root=/dev/ram rw " \
523"console=$consoledev,$baudrate $othbootargs " \
524"ramdisk_size=$ramdisk_size;" \
525"usb start;" \
526"ext2load usb 0:4 $loadaddr $bootfile;" \
527"ext2load usb 0:4 $fdtaddr $fdtfile;" \
528"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
529"bootm $loadaddr $ramdiskaddr $fdtaddr"
530
531#define CONFIG_NORBOOT \
532"setenv bootargs root=/dev/mtdblock3 rw " \
533"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
534"bootm $norbootaddr - $norfdtaddr"
535
536#define CONFIG_RAMBOOTCOMMAND_TFTP \
537"setenv bootargs root=/dev/ram rw " \
538"console=$consoledev,$baudrate $othbootargs " \
539"ramdisk_size=$ramdisk_size;" \
540"tftp $ramdiskaddr $ramdiskfile;" \
541"tftp $loadaddr $bootfile;" \
542"tftp $fdtaddr $fdtfile;" \
543"bootm $loadaddr $ramdiskaddr $fdtaddr"
544
545#define CONFIG_RAMBOOTCOMMAND \
546"setenv bootargs root=/dev/ram rw " \
547"console=$consoledev,$baudrate $othbootargs " \
548"ramdisk_size=$ramdisk_size;" \
549"bootm 0xefa80000 0xeeb80000 0xefe80000"
550
551#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
552
553#endif
554