LXR uboot/include/configs/socfpga

   1/*
   2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6#ifndef __CONFIG_SOCFPGA_COMMON_H__
   7#define __CONFIG_SOCFPGA_COMMON_H__
   8
   9/* Virtual target or real hardware */
  10#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  11
  12/*
  13 * High level configuration
  14 */
  15#define CONFIG_DISPLAY_BOARDINFO_LATE
  16#define CONFIG_CLOCKS
  17
  18#define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  19
  20#define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  21
  22/* add target to build it automatically upon "make" */
  23#define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
  24
  25/*
  26 * Memory configurations
  27 */
  28#define CONFIG_NR_DRAM_BANKS            1
  29#define PHYS_SDRAM_1                    0x0
  30#define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  31#define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  32#define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  33#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  34#define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  35#define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  36#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  37#define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  38#define CONFIG_SYS_INIT_RAM_SIZE        0x40000 /* 256KB */
  39#endif
  40#define CONFIG_SYS_INIT_SP_OFFSET               \
  41        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  42#define CONFIG_SYS_INIT_SP_ADDR                 \
  43        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  44
  45#define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  46#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  47#define CONFIG_SYS_TEXT_BASE            0x08000040
  48#else
  49#define CONFIG_SYS_TEXT_BASE            0x01000040
  50#endif
  51
  52/*
  53 * U-Boot general configurations
  54 */
  55#define CONFIG_SYS_LONGHELP
  56#define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  57#define CONFIG_SYS_PBSIZE       \
  58        (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  59                                                /* Print buffer size */
  60#define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  61#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  62                                                /* Boot argument buffer size */
  63#define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  64#define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  65
  66#ifndef CONFIG_SYS_HOSTNAME
  67#define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  68#endif
  69
  70#define CONFIG_CMD_PXE
  71#define CONFIG_MENU
  72
  73/*
  74 * Cache
  75 */
  76#define CONFIG_SYS_L2_PL310
  77#define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  78
  79/*
  80 * EPCS/EPCQx1 Serial Flash Controller
  81 */
  82#ifdef CONFIG_ALTERA_SPI
  83#define CONFIG_SF_DEFAULT_SPEED         30000000
  84/*
  85 * The base address is configurable in QSys, each board must specify the
  86 * base address based on it's particular FPGA configuration. Please note
  87 * that the address here is incremented by  0x400  from the Base address
  88 * selected in QSys, since the SPI registers are at offset +0x400.
  89 * #define CONFIG_SYS_SPI_BASE          0xff240400
  90 */
  91#endif
  92
  93/*
  94 * Ethernet on SoC (EMAC)
  95 */
  96#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
  97#define CONFIG_DW_ALTDESCRIPTOR
  98#define CONFIG_MII
  99#define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
 100#define CONFIG_PHY_GIGE
 101#endif
 102
 103/*
 104 * FPGA Driver
 105 */
 106#ifdef CONFIG_TARGET_SOCFPGA_GEN5
 107#ifdef CONFIG_CMD_FPGA
 108#define CONFIG_FPGA
 109#define CONFIG_FPGA_ALTERA
 110#define CONFIG_FPGA_SOCFPGA
 111#define CONFIG_FPGA_COUNT               1
 112#endif
 113#endif
 114/*
 115 * L4 OSC1 Timer 0
 116 */
 117/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 118#define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 119#define CONFIG_SYS_TIMER_COUNTS_DOWN
 120#define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 121#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 122#define CONFIG_SYS_TIMER_RATE           2400000
 123#else
 124#define CONFIG_SYS_TIMER_RATE           25000000
 125#endif
 126
 127/*
 128 * L4 Watchdog
 129 */
 130#ifdef CONFIG_HW_WATCHDOG
 131#define CONFIG_DESIGNWARE_WATCHDOG
 132#define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 133#define CONFIG_DW_WDT_CLOCK_KHZ         25000
 134#define CONFIG_WATCHDOG_TIMEOUT_MSECS   30000
 135#endif
 136
 137/*
 138 * MMC Driver
 139 */
 140#ifdef CONFIG_CMD_MMC
 141#define CONFIG_BOUNCE_BUFFER
 142/* FIXME */
 143/* using smaller max blk cnt to avoid flooding the limited stack we have */
 144#define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 145#endif
 146
 147/*
 148 * NAND Support
 149 */
 150#ifdef CONFIG_NAND_DENALI
 151#define CONFIG_SYS_MAX_NAND_DEVICE      1
 152#define CONFIG_SYS_NAND_MAX_CHIPS       1
 153#define CONFIG_SYS_NAND_ONFI_DETECTION
 154#define CONFIG_NAND_DENALI_ECC_SIZE     512
 155#define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 156#define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 157#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_DATA_BASE + 0x10)
 158#endif
 159
 160/*
 161 * I2C support
 162 */
 163#define CONFIG_SYS_I2C
 164#define CONFIG_SYS_I2C_BUS_MAX          4
 165#define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 166#define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 167#define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 168#define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 169/* Using standard mode which the speed up to 100Kb/s */
 170#define CONFIG_SYS_I2C_SPEED            100000
 171#define CONFIG_SYS_I2C_SPEED1           100000
 172#define CONFIG_SYS_I2C_SPEED2           100000
 173#define CONFIG_SYS_I2C_SPEED3           100000
 174/* Address of device when used as slave */
 175#define CONFIG_SYS_I2C_SLAVE            0x02
 176#define CONFIG_SYS_I2C_SLAVE1           0x02
 177#define CONFIG_SYS_I2C_SLAVE2           0x02
 178#define CONFIG_SYS_I2C_SLAVE3           0x02
 179#ifndef __ASSEMBLY__
 180/* Clock supplied to I2C controller in unit of MHz */
 181unsigned int cm_get_l4_sp_clk_hz(void);
 182#define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 183#endif
 184
 185/*
 186 * QSPI support
 187 */
 188/* Enable multiple SPI NOR flash manufacturers */
 189#ifndef CONFIG_SPL_BUILD
 190#define CONFIG_SPI_FLASH_MTD
 191#define CONFIG_CMD_MTDPARTS
 192#define CONFIG_MTD_DEVICE
 193#define CONFIG_MTD_PARTITIONS
 194#define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
 195#endif
 196/* QSPI reference clock */
 197#ifndef __ASSEMBLY__
 198unsigned int cm_get_qspi_controller_clk_hz(void);
 199#define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 200#endif
 201#define CONFIG_CQSPI_DECODER            0
 202#define CONFIG_BOUNCE_BUFFER
 203
 204/*
 205 * Designware SPI support
 206 */
 207
 208/*
 209 * Serial Driver
 210 */
 211#define CONFIG_SYS_NS16550_SERIAL
 212#define CONFIG_SYS_NS16550_REG_SIZE     -4
 213#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 214#define CONFIG_SYS_NS16550_CLK          1000000
 215#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
 216#define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 217#define CONFIG_SYS_NS16550_CLK          100000000
 218#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 219#define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
 220#define CONFIG_SYS_NS16550_CLK          50000000
 221#endif
 222#define CONFIG_CONS_INDEX               1
 223
 224/*
 225 * USB
 226 */
 227#ifdef CONFIG_CMD_USB
 228#define CONFIG_USB_DWC2
 229#endif
 230
 231/*
 232 * USB Gadget (DFU, UMS)
 233 */
 234#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 235#define CONFIG_USB_FUNCTION_MASS_STORAGE
 236
 237#define CONFIG_SYS_DFU_DATA_BUF_SIZE    (16 * 1024 * 1024)
 238#define DFU_DEFAULT_POLL_TIMEOUT        300
 239
 240/* USB IDs */
 241#define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 242#define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 243#endif
 244
 245/*
 246 * U-Boot environment
 247 */
 248#if !defined(CONFIG_ENV_SIZE)
 249#define CONFIG_ENV_SIZE                 (8 * 1024)
 250#endif
 251
 252/* Environment for SDMMC boot */
 253#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 254#define CONFIG_SYS_MMC_ENV_DEV          0 /* device 0 */
 255#define CONFIG_ENV_OFFSET               (34 * 512) /* just after the GPT */
 256#endif
 257
 258/* Environment for QSPI boot */
 259#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 260#define CONFIG_ENV_OFFSET               0x00100000
 261#define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 262#endif
 263
 264/*
 265 * mtd partitioning for serial NOR flash
 266 *
 267 * device nor0 <ff705000.spi.0>, # parts = 6
 268 * #: name                size            offset          mask_flags
 269 * 0: u-boot              0x00100000      0x00000000      0
 270 * 1: env1                0x00040000      0x00100000      0
 271 * 2: env2                0x00040000      0x00140000      0
 272 * 3: UBI                 0x03e80000      0x00180000      0
 273 * 4: boot                0x00e80000      0x00180000      0
 274 * 5: rootfs              0x01000000      0x01000000      0
 275 *
 276 */
 277#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
 278#define MTDPARTS_DEFAULT        "mtdparts=ff705000.spi.0:"\
 279                                "1m(u-boot),"           \
 280                                "256k(env1),"           \
 281                                "256k(env2),"           \
 282                                "14848k(boot),"         \
 283                                "16m(rootfs),"          \
 284                                "-@1536k(UBI)\0"
 285#endif
 286
 287/* UBI and UBIFS support */
 288#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
 289#define CONFIG_CMD_UBIFS
 290#define CONFIG_RBTREE
 291#define CONFIG_LZO
 292#endif
 293
 294/*
 295 * SPL
 296 *
 297 * SRAM Memory layout:
 298 *
 299 * 0xFFFF_0000 ...... Start of SRAM
 300 * 0xFFFF_xxxx ...... Top of stack (grows down)
 301 * 0xFFFF_yyyy ...... Malloc area
 302 * 0xFFFF_zzzz ...... Global Data
 303 * 0xFFFF_FF00 ...... End of SRAM
 304 */
 305#define CONFIG_SPL_FRAMEWORK
 306#define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 307#define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 308
 309/* SPL SDMMC boot support */
 310#ifdef CONFIG_SPL_MMC_SUPPORT
 311#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 312#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 313#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 314#endif
 315#else
 316#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 317#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION      1
 318#endif
 319#endif
 320
 321/* SPL QSPI boot support */
 322#ifdef CONFIG_SPL_SPI_SUPPORT
 323#define CONFIG_SPL_SPI_LOAD
 324#define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 325#endif
 326
 327/* SPL NAND boot support */
 328#ifdef CONFIG_SPL_NAND_SUPPORT
 329#define CONFIG_SYS_NAND_USE_FLASH_BBT
 330#define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 331#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 332#endif
 333
 334/*
 335 * Stack setup
 336 */
 337#define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 338
 339/* Extra Environment */
 340#ifndef CONFIG_SPL_BUILD
 341#include <config_distro_defaults.h>
 342
 343#ifdef CONFIG_CMD_PXE
 344#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 345#else
 346#define BOOT_TARGET_DEVICES_PXE(func)
 347#endif
 348
 349#ifdef CONFIG_CMD_MMC
 350#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 351#else
 352#define BOOT_TARGET_DEVICES_MMC(func)
 353#endif
 354
 355#define BOOT_TARGET_DEVICES(func) \
 356        BOOT_TARGET_DEVICES_MMC(func) \
 357        BOOT_TARGET_DEVICES_PXE(func) \
 358        func(DHCP, dhcp, na)
 359
 360#include <config_distro_bootcmd.h>
 361
 362#ifndef CONFIG_EXTRA_ENV_SETTINGS
 363#define CONFIG_EXTRA_ENV_SETTINGS \
 364        "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 365        "bootm_size=0xa000000\0" \
 366        "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
 367        "fdt_addr_r=0x02000000\0" \
 368        "scriptaddr=0x02100000\0" \
 369        "pxefile_addr_r=0x02200000\0" \
 370        "ramdisk_addr_r=0x02300000\0" \
 371        BOOTENV
 372
 373#endif
 374#endif
 375
 376#endif  /* __CONFIG_SOCFPGA_COMMON_H__ */
 377