1
2
3
4
5
6
7
8
9#ifndef _KWBIMAGE_H_
10#define _KWBIMAGE_H_
11
12#include <compiler.h>
13#include <stdint.h>
14
15#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
16#define MAX_TEMPBUF_LEN 32
17
18
19#define IBR_HDR_ECC_DEFAULT 0x00
20#define IBR_HDR_ECC_FORCED_HAMMING 0x01
21#define IBR_HDR_ECC_FORCED_RS 0x02
22#define IBR_HDR_ECC_DISABLED 0x03
23
24
25#define IBR_HDR_I2C_ID 0x4D
26#define IBR_HDR_SPI_ID 0x5A
27#define IBR_HDR_NAND_ID 0x8B
28#define IBR_HDR_SATA_ID 0x78
29#define IBR_HDR_PEX_ID 0x9C
30#define IBR_HDR_UART_ID 0x69
31#define IBR_DEF_ATTRIB 0x00
32
33#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
34
35
36struct main_hdr_v0 {
37 uint8_t blockid;
38 uint8_t nandeccmode;
39 uint16_t nandpagesize;
40 uint32_t blocksize;
41 uint32_t rsvd1;
42 uint32_t srcaddr;
43 uint32_t destaddr;
44 uint32_t execaddr;
45 uint8_t satapiomode;
46 uint8_t rsvd3;
47 uint16_t ddrinitdelay;
48 uint16_t rsvd2;
49 uint8_t ext;
50 uint8_t checksum;
51};
52
53struct ext_hdr_v0_reg {
54 uint32_t raddr;
55 uint32_t rdata;
56};
57
58#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
59
60struct ext_hdr_v0 {
61 uint32_t offset;
62 uint8_t reserved[0x20 - sizeof(uint32_t)];
63 struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
64 uint8_t reserved2[7];
65 uint8_t checksum;
66};
67
68struct kwb_header {
69 struct main_hdr_v0 kwb_hdr;
70 struct ext_hdr_v0 kwb_exthdr;
71};
72
73
74struct main_hdr_v1 {
75 uint8_t blockid;
76 uint8_t flags;
77 uint16_t reserved2;
78 uint32_t blocksize;
79 uint8_t version;
80 uint8_t headersz_msb;
81 uint16_t headersz_lsb;
82 uint32_t srcaddr;
83 uint32_t destaddr;
84 uint32_t execaddr;
85 uint8_t options;
86 uint8_t nandblocksize;
87 uint8_t nandbadblklocation;
88 uint8_t reserved4;
89 uint16_t reserved5;
90 uint8_t ext;
91 uint8_t checksum;
92};
93
94
95
96
97#define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0
98#define MAIN_HDR_V1_OPT_BAUD_2400 0x1
99#define MAIN_HDR_V1_OPT_BAUD_4800 0x2
100#define MAIN_HDR_V1_OPT_BAUD_9600 0x3
101#define MAIN_HDR_V1_OPT_BAUD_19200 0x4
102#define MAIN_HDR_V1_OPT_BAUD_38400 0x5
103#define MAIN_HDR_V1_OPT_BAUD_57600 0x6
104#define MAIN_HDR_V1_OPT_BAUD_115200 0x7
105
106
107
108
109struct opt_hdr_v1 {
110 uint8_t headertype;
111 uint8_t headersz_msb;
112 uint16_t headersz_lsb;
113 char data[0];
114};
115
116
117
118
119struct pubkey_der_v1 {
120 uint8_t key[524];
121};
122
123
124
125
126struct sig_v1 {
127 uint8_t sig[256];
128};
129
130
131
132
133struct secure_hdr_v1 {
134 uint8_t headertype;
135 uint8_t headersz_msb;
136 uint16_t headersz_lsb;
137 uint32_t reserved1;
138 struct pubkey_der_v1 kak;
139 uint8_t jtag_delay;
140 uint8_t reserved2;
141 uint16_t reserved3;
142 uint32_t boxid;
143 uint32_t flashid;
144 struct sig_v1 hdrsig;
145 struct sig_v1 imgsig;
146 struct pubkey_der_v1 csk[16];
147 struct sig_v1 csksig;
148 uint8_t next;
149 uint8_t reserved4;
150 uint16_t reserved5;
151};
152
153
154
155
156
157
158
159
160
161
162
163#define OPT_HDR_V1_SECURE_TYPE 0x1
164#define OPT_HDR_V1_BINARY_TYPE 0x2
165#define OPT_HDR_V1_REGISTER_TYPE 0x3
166
167#define KWBHEADER_V1_SIZE(hdr) \
168 (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
169
170enum kwbimage_cmd {
171 CMD_INVALID,
172 CMD_BOOT_FROM,
173 CMD_NAND_ECC_MODE,
174 CMD_NAND_PAGE_SIZE,
175 CMD_SATA_PIO_MODE,
176 CMD_DDR_INIT_DELAY,
177 CMD_DATA
178};
179
180enum kwbimage_cmd_types {
181 CFG_INVALID = -1,
182 CFG_COMMAND,
183 CFG_DATA0,
184 CFG_DATA1
185};
186
187
188
189
190void init_kwb_image_type (void);
191
192
193
194
195
196
197static inline unsigned int image_version(void *header)
198{
199 unsigned char *ptr = header;
200 return ptr[8];
201}
202
203#endif
204