LXR uboot/arch/arm/cpu/arm926ejs/lpc32xx/devices.c

   1/*
   2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <dm.h>
   9#include <ns16550.h>
  10#include <dm/platform_data/lpc32xx_hsuart.h>
  11
  12#include <asm/arch/clk.h>
  13#include <asm/arch/uart.h>
  14#include <asm/arch/mux.h>
  15#include <asm/io.h>
  16
  17static struct clk_pm_regs    *clk  = (struct clk_pm_regs *)CLK_PM_BASE;
  18static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
  19static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
  20
  21void lpc32xx_uart_init(unsigned int uart_id)
  22{
  23        if (uart_id < 1 || uart_id > 7)
  24                return;
  25
  26        /* Disable loopback mode, if it is set by S1L bootloader */
  27        clrbits_le32(&ctrl->loop,
  28                     UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
  29
  30        if (uart_id < 3 || uart_id > 6)
  31                return;
  32
  33        /* Enable UART system clock */
  34        setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
  35
  36        /* Set UART into autoclock mode */
  37        clrsetbits_le32(&ctrl->clkmode,
  38                        UART_CLKMODE_MASK(uart_id),
  39                        UART_CLKMODE_AUTO(uart_id));
  40
  41        /* Bypass pre-divider of UART clock */
  42        writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
  43               &clk->u3clk + (uart_id - 3));
  44}
  45
  46#if !CONFIG_IS_ENABLED(OF_CONTROL)
  47static const struct ns16550_platdata lpc32xx_uart[] = {
  48        { .base = UART3_BASE, .reg_shift = 2,
  49          .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  50        { .base = UART4_BASE, .reg_shift = 2,
  51          .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  52        { .base = UART5_BASE, .reg_shift = 2,
  53          .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  54        { .base = UART6_BASE, .reg_shift = 2,
  55          .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  56};
  57
  58#if defined(CONFIG_LPC32XX_HSUART)
  59static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
  60        { HS_UART1_BASE, },
  61        { HS_UART2_BASE, },
  62        { HS_UART7_BASE, },
  63};
  64#endif
  65
  66U_BOOT_DEVICES(lpc32xx_uarts) = {
  67#if defined(CONFIG_LPC32XX_HSUART)
  68        { "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
  69        { "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
  70#endif
  71        { "ns16550_serial", &lpc32xx_uart[0], },
  72        { "ns16550_serial", &lpc32xx_uart[1], },
  73        { "ns16550_serial", &lpc32xx_uart[2], },
  74        { "ns16550_serial", &lpc32xx_uart[3], },
  75#if defined(CONFIG_LPC32XX_HSUART)
  76        { "lpc32xx_hsuart", &lpc32xx_hsuart[2], },
  77#endif
  78};
  79#endif
  80
  81void lpc32xx_dma_init(void)
  82{
  83        /* Enable DMA interface */
  84        writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
  85}
  86
  87void lpc32xx_mac_init(void)
  88{
  89        /* Enable MAC interface */
  90        writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
  91#if defined(CONFIG_RMII)
  92                | CLK_MAC_RMII,
  93#else
  94                | CLK_MAC_MII,
  95#endif
  96                &clk->macclk_ctrl);
  97}
  98
  99void lpc32xx_mlc_nand_init(void)
 100{
 101        /* Enable NAND interface */
 102        writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
 103}
 104
 105void lpc32xx_slc_nand_init(void)
 106{
 107        /* Enable SLC NAND interface */
 108        writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
 109}
 110
 111void lpc32xx_usb_init(void)
 112{
 113        /* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
 114        clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
 115}
 116
 117void lpc32xx_i2c_init(unsigned int devnum)
 118{
 119        /* Enable I2C interface */
 120        uint32_t ctrl = readl(&clk->i2cclk_ctrl);
 121        if (devnum == 1)
 122                ctrl |= CLK_I2C1_ENABLE;
 123        if (devnum == 2)
 124                ctrl |= CLK_I2C2_ENABLE;
 125        writel(ctrl, &clk->i2cclk_ctrl);
 126}
 127
 128U_BOOT_DEVICE(lpc32xx_gpios) = {
 129        .name = "gpio_lpc32xx"
 130};
 131
 132/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
 133
 134#define P_MUX_SET_SSP0 0x1600
 135
 136void lpc32xx_ssp_init(void)
 137{
 138        /* Enable SSP0 interface */
 139        writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
 140        /* Mux SSP0 pins */
 141        writel(P_MUX_SET_SSP0, &mux->p_mux_set);
 142}
 143