1/* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6#ifndef _ASM_ARCH_SCU_AST2500_H 7#define _ASM_ARCH_SCU_AST2500_H 8 9#define SCU_UNLOCK_VALUE 0x1688a8a8 10 11#define SCU_HWSTRAP_VGAMEM_SHIFT 2 12#define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) 13#define SCU_HWSTRAP_MAC1_RGMII (1 << 6) 14#define SCU_HWSTRAP_MAC2_RGMII (1 << 7) 15#define SCU_HWSTRAP_DDR4 (1 << 24) 16#define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) 17 18#define SCU_MPLL_DENUM_SHIFT 0 19#define SCU_MPLL_DENUM_MASK 0x1f 20#define SCU_MPLL_NUM_SHIFT 5 21#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT) 22#define SCU_MPLL_POST_SHIFT 13 23#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) 24#define SCU_PCLK_DIV_SHIFT 23 25#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) 26#define SCU_HPLL_DENUM_SHIFT 0 27#define SCU_HPLL_DENUM_MASK 0x1f 28#define SCU_HPLL_NUM_SHIFT 5 29#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT) 30#define SCU_HPLL_POST_SHIFT 13 31#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT) 32 33#define SCU_MACCLK_SHIFT 16 34#define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT) 35 36#define SCU_MISC2_RGMII_HPLL (1 << 23) 37#define SCU_MISC2_RGMII_CLKDIV_SHIFT 20 38#define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT) 39#define SCU_MISC2_RMII_MPLL (1 << 19) 40#define SCU_MISC2_RMII_CLKDIV_SHIFT 16 41#define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT) 42#define SCU_MISC2_UARTCLK_SHIFT 24 43 44#define SCU_MISC_D2PLL_OFF (1 << 4) 45#define SCU_MISC_UARTCLK_DIV13 (1 << 12) 46#define SCU_MISC_GCRT_USB20CLK (1 << 21) 47 48#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0 49#define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\ 50 << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) 51#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6 52#define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\ 53 << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT) 54#define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12 55#define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT) 56#define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18 57#define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT) 58#define SCU_MICDS_MAC1RMII_TXFALL (1 << 24) 59#define SCU_MICDS_MAC2RMII_TXFALL (1 << 25) 60#define SCU_MICDS_RMII1_RCLKEN (1 << 29) 61#define SCU_MICDS_RMII2_RCLKEN (1 << 30) 62#define SCU_MICDS_RGMIIPLL (1 << 31) 63 64/* 65 * SYSRESET is actually more like a Power register, 66 * except that corresponding bit set to 1 means that 67 * the peripheral is off. 68 */ 69#define SCU_SYSRESET_XDMA (1 << 25) 70#define SCU_SYSRESET_MCTP (1 << 24) 71#define SCU_SYSRESET_ADC (1 << 23) 72#define SCU_SYSRESET_JTAG (1 << 22) 73#define SCU_SYSRESET_MIC (1 << 18) 74#define SCU_SYSRESET_SDIO (1 << 16) 75#define SCU_SYSRESET_USB11HOST (1 << 15) 76#define SCU_SYSRESET_USBHUB (1 << 14) 77#define SCU_SYSRESET_CRT (1 << 13) 78#define SCU_SYSRESET_MAC2 (1 << 12) 79#define SCU_SYSRESET_MAC1 (1 << 11) 80#define SCU_SYSRESET_PECI (1 << 10) 81#define SCU_SYSRESET_PWM (1 << 9) 82#define SCU_SYSRESET_PCI_VGA (1 << 8) 83#define SCU_SYSRESET_2D (1 << 7) 84#define SCU_SYSRESET_VIDEO (1 << 6) 85#define SCU_SYSRESET_LPC (1 << 5) 86#define SCU_SYSRESET_HAC (1 << 4) 87#define SCU_SYSRESET_USBHID (1 << 3) 88#define SCU_SYSRESET_I2C (1 << 2) 89#define SCU_SYSRESET_AHB (1 << 1) 90#define SCU_SYSRESET_SDRAM_WDT (1 << 0) 91 92/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */ 93#define SCU_PINMUX_CTRL5_I2C (1 << 16) 94 95/* 96 * The values are grouped by function, not by register. 97 * They are actually scattered across multiple loosely related registers. 98 */ 99#define SCU_PIN_FUN_MAC1_MDC (1 << 30) 100#define SCU_PIN_FUN_MAC1_MDIO (1 << 31) 101#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0) 102#define SCU_PIN_FUN_MAC2_MDIO (1 << 2) 103#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1) 104#define SCU_PIN_FUN_SCL1 (1 << 12) 105#define SCU_PIN_FUN_SCL2 (1 << 14) 106#define SCU_PIN_FUN_SDA1 (1 << 13) 107#define SCU_PIN_FUN_SDA2 (1 << 15) 108 109#define SCU_CLKSTOP_MAC1 (1 << 20) 110#define SCU_CLKSTOP_MAC2 (1 << 21) 111 112#define SCU_D2PLL_EXT1_OFF (1 << 0) 113#define SCU_D2PLL_EXT1_BYPASS (1 << 1) 114#define SCU_D2PLL_EXT1_RESET (1 << 2) 115#define SCU_D2PLL_EXT1_MODE_SHIFT 3 116#define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT) 117#define SCU_D2PLL_EXT1_PARAM_SHIFT 5 118#define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT) 119 120#define SCU_D2PLL_NUM_SHIFT 0 121#define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT) 122#define SCU_D2PLL_DENUM_SHIFT 8 123#define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT) 124#define SCU_D2PLL_POST_SHIFT 13 125#define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT) 126#define SCU_D2PLL_ODIV_SHIFT 19 127#define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT) 128#define SCU_D2PLL_SIC_SHIFT 22 129#define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT) 130#define SCU_D2PLL_SIP_SHIFT 27 131#define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT) 132 133#define SCU_CLKDUTY_DCLK_SHIFT 0 134#define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT) 135#define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8 136#define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT) 137#define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16 138#define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) 139 140#ifndef __ASSEMBLY__ 141 142struct ast2500_clk_priv { 143 struct ast2500_scu *scu; 144}; 145 146struct ast2500_scu { 147 u32 protection_key; 148 u32 sysreset_ctrl1; 149 u32 clk_sel1; 150 u32 clk_stop_ctrl1; 151 u32 freq_counter_ctrl; 152 u32 freq_counter_cmp; 153 u32 intr_ctrl; 154 u32 d2_pll_param; 155 u32 m_pll_param; 156 u32 h_pll_param; 157 u32 d_pll_param; 158 u32 misc_ctrl1; 159 u32 pci_config[3]; 160 u32 sysreset_status; 161 u32 vga_handshake[2]; 162 u32 mac_clk_delay; 163 u32 misc_ctrl2; 164 u32 vga_scratch[8]; 165 u32 hwstrap; 166 u32 rng_ctrl; 167 u32 rng_data; 168 u32 rev_id; 169 u32 pinmux_ctrl[6]; 170 u32 reserved0; 171 u32 extrst_sel; 172 u32 pinmux_ctrl1[4]; 173 u32 reserved1[2]; 174 u32 mac_clk_delay_100M; 175 u32 mac_clk_delay_10M; 176 u32 wakeup_enable; 177 u32 wakeup_control; 178 u32 reserved2[3]; 179 u32 sysreset_ctrl2; 180 u32 clk_sel2; 181 u32 clk_stop_ctrl2; 182 u32 freerun_counter; 183 u32 freerun_counter_ext; 184 u32 clk_duty_meas_ctrl; 185 u32 clk_duty_meas_res; 186 u32 reserved3[4]; 187 /* The next registers are not key-protected */ 188 struct ast2500_cpu2 { 189 u32 ctrl; 190 u32 base_addr[9]; 191 u32 cache_ctrl; 192 } cpu2; 193 u32 reserved4; 194 u32 d_pll_ext_param[3]; 195 u32 d2_pll_ext_param[3]; 196 u32 mh_pll_ext_param; 197 u32 reserved5; 198 u32 chip_id[2]; 199 u32 reserved6[2]; 200 u32 uart_clk_ctrl; 201 u32 reserved7[7]; 202 u32 pcie_config; 203 u32 mmio_decode; 204 u32 reloc_ctrl_decode[2]; 205 u32 mailbox_addr; 206 u32 shared_sram_decode[2]; 207 u32 bmc_rev_id; 208 u32 reserved8; 209 u32 bmc_device_id; 210 u32 reserved9[13]; 211 u32 clk_duty_sel; 212}; 213 214/** 215 * ast_get_clk() - get a pointer to Clock Driver 216 * 217 * @devp, OUT - pointer to Clock Driver 218 * @return zero on success, error code (< 0) otherwise. 219 */ 220int ast_get_clk(struct udevice **devp); 221 222/** 223 * ast_get_scu() - get a pointer to SCU registers 224 * 225 * @return pointer to struct ast2500_scu on success, ERR_PTR otherwise 226 */ 227void *ast_get_scu(void); 228 229/** 230 * ast_scu_unlock() - unlock protected registers 231 * 232 * @scu, pointer to ast2500_scu 233 */ 234void ast_scu_unlock(struct ast2500_scu *scu); 235 236/** 237 * ast_scu_lock() - lock protected registers 238 * 239 * @scu, pointer to ast2500_scu 240 */ 241void ast_scu_lock(struct ast2500_scu *scu); 242 243#endif /* __ASSEMBLY__ */ 244 245#endif /* _ASM_ARCH_SCU_AST2500_H */ 246