1/* 2 * Copyright 2014, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef _ASM_ARMV7_LS102XA_CONFIG_ 8#define _ASM_ARMV7_LS102XA_CONFIG_ 9 10#define OCRAM_BASE_ADDR 0x10000000 11#define OCRAM_SIZE 0x00010000 12#define OCRAM_BASE_S_ADDR 0x10010000 13#define OCRAM_S_SIZE 0x00010000 14 15#define CONFIG_SYS_IMMR 0x01000000 16#define CONFIG_SYS_DCSRBAR 0x20000000 17 18#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) 19#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000) 20 21#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) 22#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 23#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) 24#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 25#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 26#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 27#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 28#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) 29#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) 30#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) 31#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) 32#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 33#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 34#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 35#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) 36#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 37#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) 38#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) 39#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) 40#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) 41 42#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 43#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 44#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 45#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 46#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 47#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 48 49#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 50#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 51 52#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) 53 54#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 55#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 56#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 57 58#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 59 60#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 61#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 62 63#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 64 65#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 66#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 67 68#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL 69#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL 70#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL 71#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL 72#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ 73/* 74 * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) 75 * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. 76 */ 77#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ 78 CONFIG_SYS_PCIE1_VIRT_ADDR) 79#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ 80 CONFIG_SYS_PCIE2_VIRT_ADDR) 81 82/* SATA */ 83#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 84#define CONFIG_LIBATA 85#define CONFIG_SCSI_AHCI 86#define CONFIG_SCSI_AHCI_PLAT 87#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 88#define CONFIG_SYS_SCSI_MAX_LUN 1 89#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 90 CONFIG_SYS_SCSI_MAX_LUN) 91#ifdef CONFIG_DDR_SPD 92#define CONFIG_VERY_BIG_RAM 93#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 94#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE 95#endif 96 97#define CONFIG_SYS_FSL_IFC_BE 98#define CONFIG_SYS_FSL_ESDHC_BE 99#define CONFIG_SYS_FSL_WDOG_BE 100#define CONFIG_SYS_FSL_DSPI_BE 101#define CONFIG_SYS_FSL_QSPI_BE 102#define CONFIG_SYS_FSL_DCU_BE 103#define CONFIG_SYS_FSL_SEC_MON_LE 104#define CONFIG_SYS_FSL_SFP_VER_3_2 105#define CONFIG_SYS_FSL_SFP_BE 106#define CONFIG_SYS_FSL_SRK_LE 107 108#define DCU_LAYER_MAX_NUM 16 109 110#ifdef CONFIG_ARCH_LS1021A 111#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 112#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 113#else 114#error SoC not defined 115#endif 116 117#define FSL_IFC_COMPAT "fsl,ifc" 118#define FSL_QSPI_COMPAT "fsl,ls1021a-qspi" 119#define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi" 120 121#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ 122