LXR uboot/arch/arm/include/asm/arch-rockchip/cru

   1/*
   2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#ifndef __ASM_ARCH_CRU_RK3399_H_
   8#define __ASM_ARCH_CRU_RK3399_H_
   9
  10#include <common.h>
  11
  12/* Private data for the clock driver - used by rockchip_get_cru() */
  13struct rk3399_clk_priv {
  14        struct rk3399_cru *cru;
  15};
  16
  17struct rk3399_pmuclk_priv {
  18        struct rk3399_pmucru *pmucru;
  19};
  20
  21struct rk3399_pmucru {
  22        u32 ppll_con[6];
  23        u32 reserved[0x1a];
  24        u32 pmucru_clksel[6];
  25        u32 pmucru_clkfrac_con[2];
  26        u32 reserved2[0x18];
  27        u32 pmucru_clkgate_con[3];
  28        u32 reserved3;
  29        u32 pmucru_softrst_con[2];
  30        u32 reserved4[2];
  31        u32 pmucru_rstnhold_con[2];
  32        u32 reserved5[2];
  33        u32 pmucru_gatedis_con[2];
  34};
  35check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
  36
  37struct rk3399_cru {
  38        u32 apll_l_con[6];
  39        u32 reserved[2];
  40        u32 apll_b_con[6];
  41        u32 reserved1[2];
  42        u32 dpll_con[6];
  43        u32 reserved2[2];
  44        u32 cpll_con[6];
  45        u32 reserved3[2];
  46        u32 gpll_con[6];
  47        u32 reserved4[2];
  48        u32 npll_con[6];
  49        u32 reserved5[2];
  50        u32 vpll_con[6];
  51        u32 reserved6[0x0a];
  52        u32 clksel_con[108];
  53        u32 reserved7[0x14];
  54        u32 clkgate_con[35];
  55        u32 reserved8[0x1d];
  56        u32 softrst_con[21];
  57        u32 reserved9[0x2b];
  58        u32 glb_srst_fst_value;
  59        u32 glb_srst_snd_value;
  60        u32 glb_cnt_th;
  61        u32 misc_con;
  62        u32 glb_rst_con;
  63        u32 glb_rst_st;
  64        u32 reserved10[0x1a];
  65        u32 sdmmc_con[2];
  66        u32 sdio0_con[2];
  67        u32 sdio1_con[2];
  68};
  69check_member(rk3399_cru, sdio1_con[1], 0x594);
  70#define MHz             1000000
  71#define KHz             1000
  72#define OSC_HZ          (24*MHz)
  73#define APLL_HZ         (600*MHz)
  74#define GPLL_HZ         (594*MHz)
  75#define CPLL_HZ         (384*MHz)
  76#define PPLL_HZ         (676*MHz)
  77
  78#define PMU_PCLK_HZ     (48*MHz)
  79
  80#define ACLKM_CORE_HZ   (300*MHz)
  81#define ATCLK_CORE_HZ   (300*MHz)
  82#define PCLK_DBG_HZ     (100*MHz)
  83
  84#define PERIHP_ACLK_HZ  (148500*KHz)
  85#define PERIHP_HCLK_HZ  (148500*KHz)
  86#define PERIHP_PCLK_HZ  (37125*KHz)
  87
  88#define PERILP0_ACLK_HZ (99000*KHz)
  89#define PERILP0_HCLK_HZ (99000*KHz)
  90#define PERILP0_PCLK_HZ (49500*KHz)
  91
  92#define PERILP1_HCLK_HZ (99000*KHz)
  93#define PERILP1_PCLK_HZ (49500*KHz)
  94
  95#define PWM_CLOCK_HZ    PMU_PCLK_HZ
  96
  97enum apll_l_frequencies {
  98        APLL_L_1600_MHZ,
  99        APLL_L_600_MHZ,
 100};
 101
 102#endif  /* __ASM_ARCH_CRU_RK3399_H_ */
 103