1/* 2 * Sun6i platform dram controller register and constant defines 3 * 4 * (C) Copyright 2007-2012 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * Berg Xing <bergxing@allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14#ifndef _SUNXI_DRAM_SUN6I_H 15#define _SUNXI_DRAM_SUN6I_H 16 17struct sunxi_mctl_com_reg { 18 u32 cr; /* 0x00 */ 19 u32 ccr; /* 0x04 controller configuration register */ 20 u32 dbgcr; /* 0x08 */ 21 u32 dbgcr1; /* 0x0c */ 22 u32 rmcr[8]; /* 0x10 */ 23 u32 mmcr[16]; /* 0x30 */ 24 u32 mbagcr[6]; /* 0x70 */ 25 u32 maer; /* 0x88 */ 26 u8 res0[0x14]; /* 0x8c */ 27 u32 mdfscr; /* 0x100 */ 28 u32 mdfsmer; /* 0x104 */ 29 u32 mdfsmrmr; /* 0x108 */ 30 u32 mdfstr0; /* 0x10c */ 31 u32 mdfstr1; /* 0x110 */ 32 u32 mdfstr2; /* 0x114 */ 33 u32 mdfstr3; /* 0x118 */ 34 u32 mdfsgcr; /* 0x11c */ 35 u8 res1[0x1c]; /* 0x120 */ 36 u32 mdfsivr; /* 0x13c */ 37 u8 res2[0x0c]; /* 0x140 */ 38 u32 mdfstcr; /* 0x14c */ 39}; 40 41struct sunxi_mctl_ctl_reg { 42 u8 res0[0x04]; /* 0x00 */ 43 u32 sctl; /* 0x04 */ 44 u32 sstat; /* 0x08 */ 45 u8 res1[0x34]; /* 0x0c */ 46 u32 mcmd; /* 0x40 */ 47 u8 res2[0x08]; /* 0x44 */ 48 u32 cmdstat; /* 0x4c */ 49 u32 cmdstaten; /* 0x50 */ 50 u8 res3[0x0c]; /* 0x54 */ 51 u32 mrrcfg0; /* 0x60 */ 52 u32 mrrstat0; /* 0x64 */ 53 u32 mrrstat1; /* 0x68 */ 54 u8 res4[0x10]; /* 0x6c */ 55 u32 mcfg1; /* 0x7c */ 56 u32 mcfg; /* 0x80 */ 57 u32 ppcfg; /* 0x84 */ 58 u32 mstat; /* 0x88 */ 59 u32 lp2zqcfg; /* 0x8c */ 60 u8 res5[0x04]; /* 0x90 */ 61 u32 dtustat; /* 0x94 */ 62 u32 dtuna; /* 0x98 */ 63 u32 dtune; /* 0x9c */ 64 u32 dtuprd0; /* 0xa0 */ 65 u32 dtuprd1; /* 0xa4 */ 66 u32 dtuprd2; /* 0xa8 */ 67 u32 dtuprd3; /* 0xac */ 68 u32 dtuawdt; /* 0xb0 */ 69 u8 res6[0x0c]; /* 0xb4 */ 70 u32 togcnt1u; /* 0xc0 */ 71 u8 res7[0x08]; /* 0xc4 */ 72 u32 togcnt100n; /* 0xcc */ 73 u32 trefi; /* 0xd0 */ 74 u32 tmrd; /* 0xd4 */ 75 u32 trfc; /* 0xd8 */ 76 u32 trp; /* 0xdc */ 77 u32 trtw; /* 0xe0 */ 78 u32 tal; /* 0xe4 */ 79 u32 tcl; /* 0xe8 */ 80 u32 tcwl; /* 0xec */ 81 u32 tras; /* 0xf0 */ 82 u32 trc; /* 0xf4 */ 83 u32 trcd; /* 0xf8 */ 84 u32 trrd; /* 0xfc */ 85 u32 trtp; /* 0x100 */ 86 u32 twr; /* 0x104 */ 87 u32 twtr; /* 0x108 */ 88 u32 texsr; /* 0x10c */ 89 u32 txp; /* 0x110 */ 90 u32 txpdll; /* 0x114 */ 91 u32 tzqcs; /* 0x118 */ 92 u32 tzqcsi; /* 0x11c */ 93 u32 tdqs; /* 0x120 */ 94 u32 tcksre; /* 0x124 */ 95 u32 tcksrx; /* 0x128 */ 96 u32 tcke; /* 0x12c */ 97 u32 tmod; /* 0x130 */ 98 u32 trstl; /* 0x134 */ 99 u32 tzqcl; /* 0x138 */ 100 u32 tmrr; /* 0x13c */ 101 u32 tckesr; /* 0x140 */ 102 u32 tdpd; /* 0x144 */ 103 u8 res8[0xb8]; /* 0x148 */ 104 u32 dtuwactl; /* 0x200 */ 105 u32 dturactl; /* 0x204 */ 106 u32 dtucfg; /* 0x208 */ 107 u32 dtuectl; /* 0x20c */ 108 u32 dtuwd0; /* 0x210 */ 109 u32 dtuwd1; /* 0x214 */ 110 u32 dtuwd2; /* 0x218 */ 111 u32 dtuwd3; /* 0x21c */ 112 u32 dtuwdm; /* 0x220 */ 113 u32 dturd0; /* 0x224 */ 114 u32 dturd1; /* 0x228 */ 115 u32 dturd2; /* 0x22c */ 116 u32 dturd3; /* 0x230 */ 117 u32 dtulfsrwd; /* 0x234 */ 118 u32 dtulfsrrd; /* 0x238 */ 119 u32 dtueaf; /* 0x23c */ 120 u32 dfitctldly; /* 0x240 */ 121 u32 dfiodtcfg; /* 0x244 */ 122 u32 dfiodtcfg1; /* 0x248 */ 123 u32 dfiodtrmap; /* 0x24c */ 124 u32 dfitphywrd; /* 0x250 */ 125 u32 dfitphywrl; /* 0x254 */ 126 u8 res9[0x08]; /* 0x258 */ 127 u32 dfitrdden; /* 0x260 */ 128 u32 dfitphyrdl; /* 0x264 */ 129 u8 res10[0x08]; /* 0x268 */ 130 u32 dfitphyupdtype0; /* 0x270 */ 131 u32 dfitphyupdtype1; /* 0x274 */ 132 u32 dfitphyupdtype2; /* 0x278 */ 133 u32 dfitphyupdtype3; /* 0x27c */ 134 u32 dfitctrlupdmin; /* 0x280 */ 135 u32 dfitctrlupdmax; /* 0x284 */ 136 u32 dfitctrlupddly; /* 0x288 */ 137 u8 res11[4]; /* 0x28c */ 138 u32 dfiupdcfg; /* 0x290 */ 139 u32 dfitrefmski; /* 0x294 */ 140 u32 dfitcrlupdi; /* 0x298 */ 141 u8 res12[0x10]; /* 0x29c */ 142 u32 dfitrcfg0; /* 0x2ac */ 143 u32 dfitrstat0; /* 0x2b0 */ 144 u32 dfitrwrlvlen; /* 0x2b4 */ 145 u32 dfitrrdlvlen; /* 0x2b8 */ 146 u32 dfitrrdlvlgateen; /* 0x2bc */ 147 u8 res13[0x04]; /* 0x2c0 */ 148 u32 dfistcfg0; /* 0x2c4 */ 149 u32 dfistcfg1; /* 0x2c8 */ 150 u8 res14[0x04]; /* 0x2cc */ 151 u32 dfitdramclken; /* 0x2d0 */ 152 u32 dfitdramclkdis; /* 0x2d4 */ 153 u8 res15[0x18]; /* 0x2d8 */ 154 u32 dfilpcfg0; /* 0x2f0 */ 155}; 156 157struct sunxi_mctl_phy_reg { 158 u8 res0[0x04]; /* 0x00 */ 159 u32 pir; /* 0x04 */ 160 u32 pgcr; /* 0x08 phy general configuration register */ 161 u32 pgsr; /* 0x0c */ 162 u32 dllgcr; /* 0x10 */ 163 u32 acdllcr; /* 0x14 */ 164 u32 ptr0; /* 0x18 */ 165 u32 ptr1; /* 0x1c */ 166 u32 ptr2; /* 0x20 */ 167 u32 aciocr; /* 0x24 */ 168 u32 dxccr; /* 0x28 DATX8 common configuration register */ 169 u32 dsgcr; /* 0x2c dram system general config register */ 170 u32 dcr; /* 0x30 */ 171 u32 dtpr0; /* 0x34 dram timing parameters register 0 */ 172 u32 dtpr1; /* 0x38 dram timing parameters register 1 */ 173 u32 dtpr2; /* 0x3c dram timing parameters register 2 */ 174 u32 mr0; /* 0x40 mode register 0 */ 175 u32 mr1; /* 0x44 mode register 1 */ 176 u32 mr2; /* 0x48 mode register 2 */ 177 u32 mr3; /* 0x4c mode register 3 */ 178 u32 odtcr; /* 0x50 */ 179 u32 dtar; /* 0x54 data training address register */ 180 u32 dtd0; /* 0x58 */ 181 u32 dtd1; /* 0x5c */ 182 u8 res1[0x60]; /* 0x60 */ 183 u32 dcuar; /* 0xc0 */ 184 u32 dcudr; /* 0xc4 */ 185 u32 dcurr; /* 0xc8 */ 186 u32 dculr; /* 0xcc */ 187 u32 dcugcr; /* 0xd0 */ 188 u32 dcutpr; /* 0xd4 */ 189 u32 dcusr0; /* 0xd8 */ 190 u32 dcusr1; /* 0xdc */ 191 u8 res2[0x20]; /* 0xe0 */ 192 u32 bistrr; /* 0x100 */ 193 u32 bistmskr0; /* 0x104 */ 194 u32 bistmskr1; /* 0x108 */ 195 u32 bistwcr; /* 0x10c */ 196 u32 bistlsr; /* 0x110 */ 197 u32 bistar0; /* 0x114 */ 198 u32 bistar1; /* 0x118 */ 199 u32 bistar2; /* 0x11c */ 200 u32 bistupdr; /* 0x120 */ 201 u32 bistgsr; /* 0x124 */ 202 u32 bistwer; /* 0x128 */ 203 u32 bistber0; /* 0x12c */ 204 u32 bistber1; /* 0x130 */ 205 u32 bistber2; /* 0x134 */ 206 u32 bistwcsr; /* 0x138 */ 207 u32 bistfwr0; /* 0x13c */ 208 u32 bistfwr1; /* 0x140 */ 209 u8 res3[0x3c]; /* 0x144 */ 210 u32 zq0cr0; /* 0x180 zq 0 control register 0 */ 211 u32 zq0cr1; /* 0x184 zq 0 control register 1 */ 212 u32 zq0sr0; /* 0x188 zq 0 status register 0 */ 213 u32 zq0sr1; /* 0x18c zq 0 status register 1 */ 214 u8 res4[0x30]; /* 0x190 */ 215 u32 dx0gcr; /* 0x1c0 */ 216 u32 dx0gsr0; /* 0x1c4 */ 217 u32 dx0gsr1; /* 0x1c8 */ 218 u32 dx0dllcr; /* 0x1cc */ 219 u32 dx0dqtr; /* 0x1d0 */ 220 u32 dx0dqstr; /* 0x1d4 */ 221 u8 res5[0x28]; /* 0x1d8 */ 222 u32 dx1gcr; /* 0x200 */ 223 u32 dx1gsr0; /* 0x204 */ 224 u32 dx1gsr1; /* 0x208 */ 225 u32 dx1dllcr; /* 0x20c */ 226 u32 dx1dqtr; /* 0x210 */ 227 u32 dx1dqstr; /* 0x214 */ 228 u8 res6[0x28]; /* 0x218 */ 229 u32 dx2gcr; /* 0x240 */ 230 u32 dx2gsr0; /* 0x244 */ 231 u32 dx2gsr1; /* 0x248 */ 232 u32 dx2dllcr; /* 0x24c */ 233 u32 dx2dqtr; /* 0x250 */ 234 u32 dx2dqstr; /* 0x254 */ 235 u8 res7[0x28]; /* 0x258 */ 236 u32 dx3gcr; /* 0x280 */ 237 u32 dx3gsr0; /* 0x284 */ 238 u32 dx3gsr1; /* 0x288 */ 239 u32 dx3dllcr; /* 0x28c */ 240 u32 dx3dqtr; /* 0x290 */ 241 u32 dx3dqstr; /* 0x294 */ 242}; 243 244/* 245 * DRAM common (sunxi_mctl_com_reg) register constants. 246 */ 247#define MCTL_CR_RANK_MASK (3 << 0) 248#define MCTL_CR_RANK(x) (((x) - 1) << 0) 249#define MCTL_CR_BANK_MASK (3 << 2) 250#define MCTL_CR_BANK(x) ((x) << 2) 251#define MCTL_CR_ROW_MASK (0xf << 4) 252#define MCTL_CR_ROW(x) (((x) - 1) << 4) 253#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) 254#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) 255#define MCTL_CR_BUSW_MASK (3 << 12) 256#define MCTL_CR_BUSW16 (1 << 12) 257#define MCTL_CR_BUSW32 (3 << 12) 258#define MCTL_CR_SEQUENCE (1 << 15) 259#define MCTL_CR_DDR3 (3 << 16) 260#define MCTL_CR_CHANNEL_MASK (1 << 19) 261#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) 262#define MCTL_CR_UNKNOWN ((1 << 22) | (1 << 20)) 263#define MCTL_CCR_CH0_CLK_EN (1 << 0) 264#define MCTL_CCR_CH1_CLK_EN (1 << 1) 265#define MCTL_CCR_MASTER_CLK_EN (1 << 2) 266 267/* 268 * DRAM control (sunxi_mctl_ctl_reg) register constants. 269 * Note that we use constant values for a lot of the timings, this is what 270 * the original boot0 bootloader does. 271 */ 272#define MCTL_SCTL_CONFIG 1 273#define MCTL_SCTL_ACCESS 2 274#define MCTL_MCMD_NOP 0x88000000 275#define MCTL_MCMD_BUSY 0x80000000 276#define MCTL_MCFG_DDR3 0x70061 277#define MCTL_TREFI 78 278#define MCTL_TMRD 4 279#define MCTL_TRFC 115 280#define MCTL_TRP 9 281#define MCTL_TPREA 0 282#define MCTL_TRTW 2 283#define MCTL_TAL 0 284#define MCTL_TCL 9 285#define MCTL_TCWL 8 286#define MCTL_TRAS 18 287#define MCTL_TRC 23 288#define MCTL_TRCD 9 289#define MCTL_TRRD 4 290#define MCTL_TRTP 4 291#define MCTL_TWR 8 292#define MCTL_TWTR 4 293#define MCTL_TEXSR 512 294#define MCTL_TXP 4 295#define MCTL_TXPDLL 14 296#define MCTL_TZQCS 64 297#define MCTL_TZQCSI 0 298#define MCTL_TDQS 1 299#define MCTL_TCKSRE 5 300#define MCTL_TCKSRX 5 301#define MCTL_TCKE 4 302#define MCTL_TMOD 12 303#define MCTL_TRSTL 80 304#define MCTL_TZQCL 512 305#define MCTL_TMRR 2 306#define MCTL_TCKESR 5 307#define MCTL_TDPD 0 308#define MCTL_DFITPHYRDL 15 309#define MCTL_DFIUPDCFG_UPD (1 << 1) 310#define MCTL_DFISTCFG0 5 311 312/* 313 * DRAM phy (sunxi_mctl_phy_reg) register values / constants. 314 */ 315#define MCTL_PIR_CLEAR_STATUS (1 << 28) 316#define MCTL_PIR_STEP1 0xe9 317#define MCTL_PIR_STEP2 0x81 318#define MCTL_PGCR_RANK (1 << 19) 319#define MCTL_PGCR 0x018c0202 320#define MCTL_PGSR_TRAIN_ERR_MASK (3 << 5) 321/* constants for both acdllcr as well as dx#dllcr */ 322#define MCTL_DLLCR_NRESET (1 << 30) 323#define MCTL_DLLCR_DISABLE (1 << 31) 324/* ptr constants these are or-ed together to get the final ptr# values */ 325#define MCTL_TITMSRST 10 326#define MCTL_TDLLLOCK 2250 327#define MCTL_TDLLSRST 23 328#define MCTL_TDINIT0 217000 329#define MCTL_TDINIT1 160 330#define MCTL_TDINIT2 87000 331#define MCTL_TDINIT3 433 332/* end ptr constants */ 333#define MCTL_ACIOCR_DISABLE ((3 << 18) | (1 << 8) | (1 << 3)) 334#define MCTL_DXCCR_DISABLE ((1 << 3) | (1 << 2)) 335#define MCTL_DXCCR 0x800 336#define MCTL_DSGCR_ENABLE (1 << 28) 337#define MCTL_DSGCR 0xf200001b 338#define MCTL_DCR_DDR3 0x0b 339/* dtpr constants these are or-ed together to get the final dtpr# values */ 340#define MCTL_TCCD 0 341#define MCTL_TDQSCKMAX 1 342#define MCTL_TDQSCK 1 343#define MCTL_TRTODT 0 344#define MCTL_TFAW 20 345#define MCTL_TAOND 0 346#define MCTL_TDLLK 512 347/* end dtpr constants */ 348#define MCTL_MR0 0x1a50 349#define MCTL_MR1 0x4 350#define MCTL_MR2 ((MCTL_TCWL - 5) << 3) 351#define MCTL_MR3 0x0 352#define MCTL_DX_GCR_EN (1 << 0) 353#define MCTL_DX_GCR 0x880 354#define MCTL_DX_GSR0_RANK0_TRAIN_DONE (1 << 0) 355#define MCTL_DX_GSR0_RANK1_TRAIN_DONE (1 << 1) 356#define MCTL_DX_GSR0_RANK0_TRAIN_ERR (1 << 4) 357#define MCTL_DX_GSR0_RANK1_TRAIN_ERR (1 << 5) 358 359#endif /* _SUNXI_DRAM_SUN6I_H */ 360