LXR uboot/arch/arm/include/asm/omap

   1/*
   2 * (C) Copyright 2008
   3 * Texas Instruments, <www.ti.com>
   4 * Syed Mohammed Khasim <khasim@ti.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation's version 2 of
  12 * the License.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#ifndef OMAP_MMC_H_
  26#define OMAP_MMC_H_
  27
  28#include <mmc.h>
  29
  30struct hsmmc {
  31        unsigned char res1[0x10];
  32        unsigned int sysconfig;         /* 0x10 */
  33        unsigned int sysstatus;         /* 0x14 */
  34        unsigned char res2[0x14];
  35        unsigned int con;               /* 0x2C */
  36        unsigned char res3[0xD4];
  37        unsigned int blk;               /* 0x104 */
  38        unsigned int arg;               /* 0x108 */
  39        unsigned int cmd;               /* 0x10C */
  40        unsigned int rsp10;             /* 0x110 */
  41        unsigned int rsp32;             /* 0x114 */
  42        unsigned int rsp54;             /* 0x118 */
  43        unsigned int rsp76;             /* 0x11C */
  44        unsigned int data;              /* 0x120 */
  45        unsigned int pstate;            /* 0x124 */
  46        unsigned int hctl;              /* 0x128 */
  47        unsigned int sysctl;            /* 0x12C */
  48        unsigned int stat;              /* 0x130 */
  49        unsigned int ie;                /* 0x134 */
  50        unsigned char res4[0x8];
  51        unsigned int capa;              /* 0x140 */
  52};
  53
  54struct omap_hsmmc_plat {
  55        struct mmc_config cfg;
  56        struct hsmmc *base_addr;
  57        struct mmc mmc;
  58        bool cd_inverted;
  59};
  60
  61/*
  62 * OMAP HS MMC Bit definitions
  63 */
  64#define MMC_SOFTRESET                   (0x1 << 1)
  65#define RESETDONE                       (0x1 << 0)
  66#define NOOPENDRAIN                     (0x0 << 0)
  67#define OPENDRAIN                       (0x1 << 0)
  68#define OD                              (0x1 << 0)
  69#define INIT_NOINIT                     (0x0 << 1)
  70#define INIT_INITSTREAM                 (0x1 << 1)
  71#define HR_NOHOSTRESP                   (0x0 << 2)
  72#define STR_BLOCK                       (0x0 << 3)
  73#define MODE_FUNC                       (0x0 << 4)
  74#define DW8_1_4BITMODE                  (0x0 << 5)
  75#define MIT_CTO                         (0x0 << 6)
  76#define CDP_ACTIVEHIGH                  (0x0 << 7)
  77#define WPP_ACTIVEHIGH                  (0x0 << 8)
  78#define RESERVED_MASK                   (0x3 << 9)
  79#define CTPL_MMC_SD                     (0x0 << 11)
  80#define BLEN_512BYTESLEN                (0x200 << 0)
  81#define NBLK_STPCNT                     (0x0 << 16)
  82#define DE_DISABLE                      (0x0 << 0)
  83#define BCE_DISABLE                     (0x0 << 1)
  84#define BCE_ENABLE                      (0x1 << 1)
  85#define ACEN_DISABLE                    (0x0 << 2)
  86#define DDIR_OFFSET                     (4)
  87#define DDIR_MASK                       (0x1 << 4)
  88#define DDIR_WRITE                      (0x0 << 4)
  89#define DDIR_READ                       (0x1 << 4)
  90#define MSBS_SGLEBLK                    (0x0 << 5)
  91#define MSBS_MULTIBLK                   (0x1 << 5)
  92#define RSP_TYPE_OFFSET                 (16)
  93#define RSP_TYPE_MASK                   (0x3 << 16)
  94#define RSP_TYPE_NORSP                  (0x0 << 16)
  95#define RSP_TYPE_LGHT136                (0x1 << 16)
  96#define RSP_TYPE_LGHT48                 (0x2 << 16)
  97#define RSP_TYPE_LGHT48B                (0x3 << 16)
  98#define CCCE_NOCHECK                    (0x0 << 19)
  99#define CCCE_CHECK                      (0x1 << 19)
 100#define CICE_NOCHECK                    (0x0 << 20)
 101#define CICE_CHECK                      (0x1 << 20)
 102#define DP_OFFSET                       (21)
 103#define DP_MASK                         (0x1 << 21)
 104#define DP_NO_DATA                      (0x0 << 21)
 105#define DP_DATA                         (0x1 << 21)
 106#define CMD_TYPE_NORMAL                 (0x0 << 22)
 107#define INDEX_OFFSET                    (24)
 108#define INDEX_MASK                      (0x3f << 24)
 109#define INDEX(i)                        (i << 24)
 110#define DATI_MASK                       (0x1 << 1)
 111#define CMDI_MASK                       (0x1 << 0)
 112#define DTW_1_BITMODE                   (0x0 << 1)
 113#define DTW_4_BITMODE                   (0x1 << 1)
 114#define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
 115#define SDBP_PWROFF                     (0x0 << 8)
 116#define SDBP_PWRON                      (0x1 << 8)
 117#define SDVS_1V8                        (0x5 << 9)
 118#define SDVS_3V0                        (0x6 << 9)
 119#define ICE_MASK                        (0x1 << 0)
 120#define ICE_STOP                        (0x0 << 0)
 121#define ICS_MASK                        (0x1 << 1)
 122#define ICS_NOTREADY                    (0x0 << 1)
 123#define ICE_OSCILLATE                   (0x1 << 0)
 124#define CEN_MASK                        (0x1 << 2)
 125#define CEN_DISABLE                     (0x0 << 2)
 126#define CEN_ENABLE                      (0x1 << 2)
 127#define CLKD_OFFSET                     (6)
 128#define CLKD_MASK                       (0x3FF << 6)
 129#define DTO_MASK                        (0xF << 16)
 130#define DTO_15THDTO                     (0xE << 16)
 131#define SOFTRESETALL                    (0x1 << 24)
 132#define CC_MASK                         (0x1 << 0)
 133#define TC_MASK                         (0x1 << 1)
 134#define BWR_MASK                        (0x1 << 4)
 135#define BRR_MASK                        (0x1 << 5)
 136#define ERRI_MASK                       (0x1 << 15)
 137#define IE_CC                           (0x01 << 0)
 138#define IE_TC                           (0x01 << 1)
 139#define IE_BWR                          (0x01 << 4)
 140#define IE_BRR                          (0x01 << 5)
 141#define IE_CTO                          (0x01 << 16)
 142#define IE_CCRC                         (0x01 << 17)
 143#define IE_CEB                          (0x01 << 18)
 144#define IE_CIE                          (0x01 << 19)
 145#define IE_DTO                          (0x01 << 20)
 146#define IE_DCRC                         (0x01 << 21)
 147#define IE_DEB                          (0x01 << 22)
 148#define IE_CERR                         (0x01 << 28)
 149#define IE_BADA                         (0x01 << 29)
 150
 151#define VS30_3V0SUP                     (1 << 25)
 152#define VS18_1V8SUP                     (1 << 26)
 153
 154/* Driver definitions */
 155#define MMCSD_SECTOR_SIZE               512
 156#define MMC_CARD                        0
 157#define SD_CARD                         1
 158#define BYTE_MODE                       0
 159#define SECTOR_MODE                     1
 160#define CLK_INITSEQ                     0
 161#define CLK_400KHZ                      1
 162#define CLK_MISC                        2
 163
 164#define RSP_TYPE_NONE   (RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
 165#define MMC_CMD0        (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 166
 167/* Clock Configurations and Macros */
 168#define MMC_CLOCK_REFERENCE     96 /* MHz */
 169
 170#define mmc_reg_out(addr, mask, val)\
 171        writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 172
 173int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 174                int wp_gpio);
 175
 176void vmmc_pbias_config(uint voltage);
 177#endif /* OMAP_MMC_H_ */
 178