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6
7#include <common.h>
8#include <clk.h>
9#include <dm.h>
10#include <ram.h>
11#include <syscon.h>
12#include <asm/io.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/cru_rk3288.h>
15#include <asm/arch/periph.h>
16#include <asm/arch/pmu_rk3288.h>
17#include <asm/arch/qos_rk3288.h>
18#include <asm/arch/boot_mode.h>
19#include <asm/gpio.h>
20#include <dm/pinctrl.h>
21#include <dt-bindings/clock/rk3288-cru.h>
22#include <power/regulator.h>
23
24DECLARE_GLOBAL_DATA_PTR;
25
26#define PMU_BASE 0xff730000
27
28static void setup_boot_mode(void)
29{
30 struct rk3288_pmu *const pmu = (void *)PMU_BASE;
31 int boot_mode = readl(&pmu->sys_reg[0]);
32
33 debug("boot mode %x.\n", boot_mode);
34
35
36 writel(BOOT_NORMAL, &pmu->sys_reg[0]);
37
38 switch (boot_mode) {
39 case BOOT_FASTBOOT:
40 printf("enter fastboot!\n");
41 env_set("preboot", "setenv preboot; fastboot usb0");
42 break;
43 case BOOT_UMS:
44 printf("enter UMS!\n");
45 env_set("preboot", "setenv preboot; if mmc dev 0;"
46 "then ums mmc 0; else ums mmc 1;fi");
47 break;
48 }
49}
50
51__weak int rk_board_late_init(void)
52{
53 return 0;
54}
55
56int rk3288_qos_init(void)
57{
58 int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
59
60 writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
61 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
62
63 if (!fdt_node_check_compatible(gd->fdt_blob, 0,
64 "rockchip,rk3288-tinker"))
65 {
66
67 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
68 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
69 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
70 }
71 return 0;
72}
73
74static void rk3288_detect_reset_reason(void)
75{
76 struct rk3288_cru *cru = rockchip_get_cru();
77 const char *reason;
78
79 if (IS_ERR(cru))
80 return;
81
82 switch (cru->cru_glb_rst_st) {
83 case GLB_POR_RST:
84 reason = "POR";
85 break;
86 case FST_GLB_RST_ST:
87 case SND_GLB_RST_ST:
88 reason = "RST";
89 break;
90 case FST_GLB_TSADC_RST_ST:
91 case SND_GLB_TSADC_RST_ST:
92 reason = "THERMAL";
93 break;
94 case FST_GLB_WDT_RST_ST:
95 case SND_GLB_WDT_RST_ST:
96 reason = "WDOG";
97 break;
98 default:
99 reason = "unknown reset";
100 }
101
102 env_set("reset_reason", reason);
103
104
105
106
107
108 rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
109}
110
111int board_late_init(void)
112{
113 setup_boot_mode();
114 rk3288_qos_init();
115 rk3288_detect_reset_reason();
116
117 return rk_board_late_init();
118}
119
120#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
121static int veyron_init(void)
122{
123 struct udevice *dev;
124 struct clk clk;
125 int ret;
126
127 ret = regulator_get_by_platname("vdd_arm", &dev);
128 if (ret) {
129 debug("Cannot set regulator name\n");
130 return ret;
131 }
132
133
134 ret = regulator_set_value(dev, 1200000);
135 if (ret)
136 return ret;
137 udelay(175);
138 ret = regulator_set_value(dev, 1400000);
139 if (ret)
140 return ret;
141 udelay(100);
142
143 ret = rockchip_get_clk(&clk.dev);
144 if (ret)
145 return ret;
146 clk.id = PLL_APLL;
147 ret = clk_set_rate(&clk, 1800000000);
148 if (IS_ERR_VALUE(ret))
149 return ret;
150
151 return 0;
152}
153#endif
154
155int board_init(void)
156{
157#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
158 struct udevice *pinctrl;
159 int ret;
160
161
162
163
164
165
166 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
167 if (ret) {
168 debug("%s: Cannot find pinctrl device\n", __func__);
169 goto err;
170 }
171 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
172 if (ret) {
173 debug("%s: Failed to set up SD card\n", __func__);
174 goto err;
175 }
176
177 return 0;
178err:
179 printf("board_init: Error %d\n", ret);
180
181
182 hang();
183
184 return -1;
185#else
186 int ret;
187
188
189 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
190 ret = veyron_init();
191 if (ret)
192 return ret;
193 }
194
195 return 0;
196#endif
197}
198
199#ifndef CONFIG_SYS_DCACHE_OFF
200void enable_caches(void)
201{
202
203 dcache_enable();
204}
205#endif
206
207#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
208#include <usb.h>
209#include <usb/dwc2_udc.h>
210
211static struct dwc2_plat_otg_data rk3288_otg_data = {
212 .rx_fifo_sz = 512,
213 .np_tx_fifo_sz = 16,
214 .tx_fifo_sz = 128,
215};
216
217int board_usb_init(int index, enum usb_init_type init)
218{
219 int node, phy_node;
220 const char *mode;
221 bool matched = false;
222 const void *blob = gd->fdt_blob;
223 u32 grf_phy_offset;
224
225
226 node = fdt_node_offset_by_compatible(blob, -1,
227 "rockchip,rk3288-usb");
228
229 while (node > 0) {
230 mode = fdt_getprop(blob, node, "dr_mode", NULL);
231 if (mode && strcmp(mode, "otg") == 0) {
232 matched = true;
233 break;
234 }
235
236 node = fdt_node_offset_by_compatible(blob, node,
237 "rockchip,rk3288-usb");
238 }
239 if (!matched) {
240 debug("Not found usb_otg device\n");
241 return -ENODEV;
242 }
243 rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
244
245 node = fdtdec_lookup_phandle(blob, node, "phys");
246 if (node <= 0) {
247 debug("Not found usb phy device\n");
248 return -ENODEV;
249 }
250
251 phy_node = fdt_parent_offset(blob, node);
252 if (phy_node <= 0) {
253 debug("Not found usb phy device\n");
254 return -ENODEV;
255 }
256
257 rk3288_otg_data.phy_of_node = phy_node;
258 grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
259
260
261 node = fdt_node_offset_by_compatible(blob, -1,
262 "rockchip,rk3288-grf");
263 if (node <= 0) {
264 debug("Not found grf device\n");
265 return -ENODEV;
266 }
267 rk3288_otg_data.regs_phy = grf_phy_offset +
268 fdtdec_get_addr(blob, node, "reg");
269
270 return dwc2_udc_probe(&rk3288_otg_data);
271}
272
273int board_usb_cleanup(int index, enum usb_init_type init)
274{
275 return 0;
276}
277#endif
278
279static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
280 char * const argv[])
281{
282 static const struct {
283 char *name;
284 int id;
285 } clks[] = {
286 { "osc", CLK_OSC },
287 { "apll", CLK_ARM },
288 { "dpll", CLK_DDR },
289 { "cpll", CLK_CODEC },
290 { "gpll", CLK_GENERAL },
291#ifdef CONFIG_ROCKCHIP_RK3036
292 { "mpll", CLK_NEW },
293#else
294 { "npll", CLK_NEW },
295#endif
296 };
297 int ret, i;
298 struct udevice *dev;
299
300 ret = rockchip_get_clk(&dev);
301 if (ret) {
302 printf("clk-uclass not found\n");
303 return 0;
304 }
305
306 for (i = 0; i < ARRAY_SIZE(clks); i++) {
307 struct clk clk;
308 ulong rate;
309
310 clk.id = clks[i].id;
311 ret = clk_request(dev, &clk);
312 if (ret < 0)
313 continue;
314
315 rate = clk_get_rate(&clk);
316 printf("%s: %lu\n", clks[i].name, rate);
317
318 clk_free(&clk);
319 }
320
321 return 0;
322}
323
324U_BOOT_CMD(
325 clock, 2, 1, do_clock,
326 "display information about clocks",
327 ""
328);
329
330#define GRF_SOC_CON2 0xff77024c
331
332int board_early_init_f(void)
333{
334 struct udevice *pinctrl;
335 struct udevice *dev;
336 int ret;
337
338
339
340
341
342
343 ret = rockchip_get_clk(&dev);
344 if (ret) {
345 debug("CLK init failed: %d\n", ret);
346 return ret;
347 }
348 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
349 if (ret) {
350 debug("%s: Cannot find pinctrl device\n", __func__);
351 return ret;
352 }
353
354
355 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
356 if (ret) {
357 debug("%s: Failed to set up console UART\n", __func__);
358 return ret;
359 }
360 rk_setreg(GRF_SOC_CON2, 1 << 0);
361
362 return 0;
363}
364
