LXR uboot/arch/arm/mach-rockchip/rk3368-board-tpl.c

   1/*
   2 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <asm/arch/clock.h>
   9#include <debug_uart.h>
  10#include <dm.h>
  11#include <ram.h>
  12#include <spl.h>
  13#include <asm/io.h>
  14#include <asm/arch/bootrom.h>
  15#include <asm/arch/cru_rk3368.h>
  16#include <asm/arch/grf_rk3368.h>
  17#include <asm/arch/hardware.h>
  18#include <asm/arch/timer.h>
  19#include <syscon.h>
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23/*
  24 * The SPL (and also the full U-Boot stage on the RK3368) will run in
  25 * secure mode (i.e. EL3) and an ATF will eventually be booted before
  26 * starting up the operating system... so we can initialize the SGRF
  27 * here and rely on the ATF installing the final (secure) policy
  28 * later.
  29 */
  30static inline uintptr_t sgrf_soc_con_addr(unsigned no)
  31{
  32        const uintptr_t SGRF_BASE =
  33                (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
  34
  35        return SGRF_BASE + sizeof(u32) * no;
  36}
  37
  38static inline uintptr_t sgrf_busdmac_addr(unsigned no)
  39{
  40        const uintptr_t SGRF_BASE =
  41                (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
  42        const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
  43        const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
  44
  45        return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
  46}
  47
  48static void sgrf_init(void)
  49{
  50        struct rk3368_cru * const cru =
  51                (struct rk3368_cru * const)rockchip_get_cru();
  52        const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
  53        const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
  54        const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
  55
  56        /* Set all configurable IP to 'non secure'-mode */
  57        rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
  58        rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
  59        rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
  60
  61        /*
  62         * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
  63         * Original comment: "ddr space set no secure mode"
  64         */
  65        rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
  66        rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
  67        rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
  68
  69        /* Set 'secure dma' to 'non secure'-mode */
  70        rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
  71        rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
  72
  73        dsb();  /* barrier */
  74
  75        rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
  76        rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
  77
  78        dsb();  /* barrier */
  79        udelay(10);
  80
  81        rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
  82        rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
  83}
  84
  85void board_debug_uart_init(void)
  86{
  87        /*
  88         * N.B.: This is called before the device-model has been
  89         *       initialised. For this reason, we can not access
  90         *       the GRF address range using the syscon API.
  91         */
  92        struct rk3368_grf * const grf =
  93                (struct rk3368_grf * const)0xff770000;
  94
  95        enum {
  96                GPIO2D1_MASK            = GENMASK(3, 2),
  97                GPIO2D1_GPIO            = 0,
  98                GPIO2D1_UART0_SOUT      = (1 << 2),
  99
 100                GPIO2D0_MASK            = GENMASK(1, 0),
 101                GPIO2D0_GPIO            = 0,
 102                GPIO2D0_UART0_SIN       = (1 << 0),
 103        };
 104
 105#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
 106        /* Enable early UART0 on the RK3368 */
 107        rk_clrsetreg(&grf->gpio2d_iomux,
 108                     GPIO2D0_MASK, GPIO2D0_UART0_SIN);
 109        rk_clrsetreg(&grf->gpio2d_iomux,
 110                     GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
 111#endif
 112}
 113
 114void board_init_f(ulong dummy)
 115{
 116        struct udevice *dev;
 117        int ret;
 118
 119#define EARLY_UART
 120#ifdef EARLY_UART
 121        /*
 122         * Debug UART can be used from here if required:
 123         *
 124         * debug_uart_init();
 125         * printch('a');
 126         * printhex8(0x1234);
 127         * printascii("string");
 128         */
 129        debug_uart_init();
 130        printascii("U-Boot TPL board init\n");
 131#endif
 132
 133        ret = spl_early_init();
 134        if (ret) {
 135                debug("spl_early_init() failed: %d\n", ret);
 136                hang();
 137        }
 138
 139        /* Reset security, so we can use DMA in the MMC drivers */
 140        sgrf_init();
 141
 142        ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 143        if (ret) {
 144                debug("DRAM init failed: %d\n", ret);
 145                return;
 146        }
 147}
 148
 149void board_return_to_bootrom(void)
 150{
 151        back_to_bootrom();
 152}
 153
 154u32 spl_boot_device(void)
 155{
 156        return BOOT_DEVICE_BOOTROM;
 157}
 158