uboot/arch/arm/mach-socfpga/scan_manager.c
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   1/*
   2 *  Copyright (C) 2013 Altera Corporation <www.altera.com>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <errno.h>
   9#include <asm/io.h>
  10#include <asm/arch/freeze_controller.h>
  11#include <asm/arch/scan_manager.h>
  12#include <asm/arch/system_manager.h>
  13
  14/*
  15 * Maximum polling loop to wait for IO scan chain engine becomes idle
  16 * to prevent infinite loop. It is important that this is NOT changed
  17 * to delay using timer functions, since at the time this function is
  18 * called, timer might not yet be inited.
  19 */
  20#define SCANMGR_MAX_DELAY               100
  21
  22/*
  23 * Maximum length of TDI_TDO packet payload is 128 bits,
  24 * represented by (length - 1) in TDI_TDO header.
  25 */
  26#define TDI_TDO_MAX_PAYLOAD             127
  27
  28#define SCANMGR_STAT_ACTIVE             (1 << 31)
  29#define SCANMGR_STAT_WFIFOCNT_MASK      0x70000000
  30
  31DECLARE_GLOBAL_DATA_PTR;
  32
  33static const struct socfpga_scan_manager *scan_manager_base =
  34                (void *)(SOCFPGA_SCANMGR_ADDRESS);
  35static const struct socfpga_freeze_controller *freeze_controller_base =
  36                (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
  37static struct socfpga_system_manager *sys_mgr_base =
  38        (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  39
  40/**
  41 * scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle
  42 * @max_iter:   Maximum number of iterations to wait for idle
  43 *
  44 * Function to check IO scan chain engine status and wait if the engine is
  45 * is active. Poll the IO scan chain engine till maximum iteration reached.
  46 */
  47static u32 scan_chain_engine_is_idle(u32 max_iter)
  48{
  49        const u32 mask = SCANMGR_STAT_ACTIVE | SCANMGR_STAT_WFIFOCNT_MASK;
  50        u32 status;
  51
  52        /* Poll the engine until the scan engine is inactive. */
  53        do {
  54                status = readl(&scan_manager_base->stat);
  55                if (!(status & mask))
  56                        return 0;
  57        } while (max_iter--);
  58
  59        return -ETIMEDOUT;
  60}
  61
  62#define JTAG_BP_INSN            (1 << 0)
  63#define JTAG_BP_TMS             (1 << 1)
  64#define JTAG_BP_PAYLOAD         (1 << 2)
  65#define JTAG_BP_2BYTE           (1 << 3)
  66#define JTAG_BP_4BYTE           (1 << 4)
  67
  68/**
  69 * scan_mgr_jtag_io() - Access the JTAG chain
  70 * @flags:      Control flags, used to configure the action on the JTAG
  71 * @iarg:       Instruction argument
  72 * @parg:       Payload argument or data
  73 *
  74 * Perform I/O on the JTAG chain
  75 */
  76static void scan_mgr_jtag_io(const u32 flags, const u8 iarg, const u32 parg)
  77{
  78        u32 data = parg;
  79
  80        if (flags & JTAG_BP_INSN) {     /* JTAG instruction */
  81                /*
  82                 * The SCC JTAG register is LSB first, so make
  83                 * space for the instruction at the LSB.
  84                 */
  85                data <<= 8;
  86                if (flags & JTAG_BP_TMS) {
  87                        data |= (0 << 7);       /* TMS instruction. */
  88                        data |= iarg & 0x3f;    /* TMS arg is 6 bits. */
  89                        if (flags & JTAG_BP_PAYLOAD)
  90                                data |= (1 << 6);
  91                } else {
  92                        data |= (1 << 7);       /* TDI/TDO instruction. */
  93                        data |= iarg & 0xf;     /* TDI/TDO arg is 4 bits. */
  94                        if (flags & JTAG_BP_PAYLOAD)
  95                                data |= (1 << 4);
  96                }
  97        }
  98
  99        if (flags & JTAG_BP_4BYTE)
 100                writel(data, &scan_manager_base->fifo_quad_byte);
 101        else if (flags & JTAG_BP_2BYTE)
 102                writel(data & 0xffff, &scan_manager_base->fifo_double_byte);
 103        else
 104                writel(data & 0xff, &scan_manager_base->fifo_single_byte);
 105}
 106
 107/**
 108 * scan_mgr_jtag_insn_data() - Send JTAG instruction and data
 109 * @iarg:       Instruction argument
 110 * @data:       Associated data
 111 * @dlen:       Length of data in bits
 112 *
 113 * This function is used when programming the IO chains to submit the
 114 * instruction followed by variable length payload.
 115 */
 116static int
 117scan_mgr_jtag_insn_data(const u8 iarg, const unsigned long *data,
 118                        const unsigned int dlen)
 119{
 120        int i, j;
 121
 122        scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_2BYTE, iarg, dlen - 1);
 123
 124        /* 32 bits or more remain */
 125        for (i = 0; i < dlen / 32; i++)
 126                scan_mgr_jtag_io(JTAG_BP_4BYTE, 0x0, data[i]);
 127
 128        if ((dlen % 32) > 24) { /* 31...24 bits remain */
 129                scan_mgr_jtag_io(JTAG_BP_4BYTE, 0x0, data[i]);
 130        } else if (dlen % 32) { /* 24...1 bit remain */
 131                for (j = 0; j < dlen % 32; j += 8)
 132                        scan_mgr_jtag_io(0, 0x0, data[i] >> j);
 133        }
 134
 135        return scan_chain_engine_is_idle(SCANMGR_MAX_DELAY);
 136}
 137
 138/**
 139 * scan_mgr_io_scan_chain_prg() - Program HPS IO Scan Chain
 140 * @io_scan_chain_id:           IO scan chain ID
 141 */
 142static int scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id)
 143{
 144        u32 io_scan_chain_len_in_bits;
 145        const unsigned long *iocsr_scan_chain;
 146        unsigned int rem, idx = 0;
 147        int ret;
 148
 149        ret = iocsr_get_config_table(io_scan_chain_id, &iocsr_scan_chain,
 150                                     &io_scan_chain_len_in_bits);
 151        if (ret)
 152                return 1;
 153
 154        /*
 155         * De-assert reinit if the IO scan chain is intended for HIO. In
 156         * this, its the chain 3.
 157         */
 158        if (io_scan_chain_id == 3)
 159                clrbits_le32(&freeze_controller_base->hioctrl,
 160                             SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
 161
 162        /*
 163         * Check if the scan chain engine is inactive and the
 164         * WFIFO is empty before enabling the IO scan chain
 165         */
 166        ret = scan_chain_engine_is_idle(SCANMGR_MAX_DELAY);
 167        if (ret)
 168                return ret;
 169
 170        /*
 171         * Enable IO Scan chain based on scan chain id
 172         * Note: only one chain can be enabled at a time
 173         */
 174        setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
 175
 176        /* Program IO scan chain. */
 177        while (io_scan_chain_len_in_bits) {
 178                if (io_scan_chain_len_in_bits > 128)
 179                        rem = 128;
 180                else
 181                        rem = io_scan_chain_len_in_bits;
 182
 183                ret = scan_mgr_jtag_insn_data(0x0, &iocsr_scan_chain[idx], rem);
 184                if (ret)
 185                        goto error;
 186                io_scan_chain_len_in_bits -= rem;
 187                idx += 4;
 188        }
 189
 190        /* Disable IO Scan chain when configuration done*/
 191        clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
 192        return 0;
 193
 194error:
 195        /* Disable IO Scan chain when error detected */
 196        clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
 197        return ret;
 198}
 199
 200int scan_mgr_configure_iocsr(void)
 201{
 202        int status = 0;
 203
 204        /* configure the IOCSR through scan chain */
 205        status |= scan_mgr_io_scan_chain_prg(0);
 206        status |= scan_mgr_io_scan_chain_prg(1);
 207        status |= scan_mgr_io_scan_chain_prg(2);
 208        status |= scan_mgr_io_scan_chain_prg(3);
 209        return status;
 210}
 211
 212/**
 213 * scan_mgr_get_fpga_id() - Obtain FPGA JTAG ID
 214 *
 215 * This function obtains JTAG ID from the FPGA TAP controller.
 216 */
 217u32 scan_mgr_get_fpga_id(void)
 218{
 219        const unsigned long data = 0;
 220        u32 id = 0xffffffff;
 221        int ret;
 222
 223        /* Enable HPS to talk to JTAG in the FPGA through the System Manager */
 224        writel(0x1, &sys_mgr_base->scanmgrgrp_ctrl);
 225
 226        /* Enable port 7 */
 227        writel(0x80, &scan_manager_base->en);
 228        /* write to CSW to make s2f_ntrst reset */
 229        writel(0x02, &scan_manager_base->stat);
 230
 231        /* Add a pause */
 232        mdelay(1);
 233
 234        /* write 0x00 to CSW to clear the s2f_ntrst */
 235        writel(0, &scan_manager_base->stat);
 236
 237        /*
 238         * Go to Test-Logic-Reset state.
 239         * This sets TAP controller into IDCODE mode.
 240         */
 241        scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_TMS, 0x1f | (1 << 5), 0x0);
 242
 243        /* Go to Run-Test/Idle -> DR-Scan -> Capture-DR -> Shift-DR state. */
 244        scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_TMS, 0x02 | (1 << 4), 0x0);
 245
 246        /*
 247         * Push 4 bytes of data through TDI->DR->TDO.
 248         *
 249         * Length of TDI data is 32bits (length - 1) and they are only
 250         * zeroes as we care only for TDO data.
 251         */
 252        ret = scan_mgr_jtag_insn_data(0x4, &data, 32);
 253        /* Read 32 bit from captured JTAG data. */
 254        if (!ret)
 255                id = readl(&scan_manager_base->fifo_quad_byte);
 256
 257        /* Disable all port */
 258        writel(0, &scan_manager_base->en);
 259        writel(0, &sys_mgr_base->scanmgrgrp_ctrl);
 260
 261        return id;
 262}
 263