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8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <ns16550.h>
12#include <usb.h>
13#include <asm/io.h>
14#include <asm/arch-tegra/ap.h>
15#include <asm/arch-tegra/board.h>
16#include <asm/arch-tegra/clk_rst.h>
17#include <asm/arch-tegra/pmc.h>
18#include <asm/arch-tegra/sys_proto.h>
19#include <asm/arch-tegra/uart.h>
20#include <asm/arch-tegra/warmboot.h>
21#include <asm/arch-tegra/gpu.h>
22#include <asm/arch-tegra/usb.h>
23#include <asm/arch-tegra/xusb-padctl.h>
24#include <asm/arch/clock.h>
25#include <asm/arch/funcmux.h>
26#include <asm/arch/pinmux.h>
27#include <asm/arch/pmu.h>
28#include <asm/arch/tegra.h>
29#ifdef CONFIG_TEGRA_CLOCK_SCALING
30#include <asm/arch/emc.h>
31#endif
32#include "emc.h"
33
34DECLARE_GLOBAL_DATA_PTR;
35
36#ifdef CONFIG_SPL_BUILD
37
38U_BOOT_DEVICE(tegra_gpios) = {
39 "gpio_tegra"
40};
41#endif
42
43__weak void pinmux_init(void) {}
44__weak void pin_mux_usb(void) {}
45__weak void pin_mux_spi(void) {}
46__weak void pin_mux_mmc(void) {}
47__weak void gpio_early_init_uart(void) {}
48__weak void pin_mux_display(void) {}
49__weak void start_cpu_fan(void) {}
50
51#if defined(CONFIG_TEGRA_NAND)
52__weak void pin_mux_nand(void)
53{
54 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
55}
56#endif
57
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61
62static void power_det_init(void)
63{
64#if defined(CONFIG_TEGRA20)
65 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
66
67
68 writel(0, &pmc->pmc_pwr_det_latch);
69 writel(0, &pmc->pmc_pwr_det);
70#endif
71}
72
73__weak int tegra_board_id(void)
74{
75 return -1;
76}
77
78#ifdef CONFIG_DISPLAY_BOARDINFO
79int checkboard(void)
80{
81 int board_id = tegra_board_id();
82
83 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
84 if (board_id != -1)
85 printf(", ID: %d\n", board_id);
86 printf("\n");
87
88 return 0;
89}
90#endif
91
92__weak int tegra_lcd_pmic_init(int board_it)
93{
94 return 0;
95}
96
97__weak int nvidia_board_init(void)
98{
99 return 0;
100}
101
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105
106int board_init(void)
107{
108 __maybe_unused int err;
109 __maybe_unused int board_id;
110
111
112 clock_init();
113 clock_verify();
114
115 tegra_gpu_config();
116
117#ifdef CONFIG_TEGRA_SPI
118 pin_mux_spi();
119#endif
120
121#ifdef CONFIG_MMC_SDHCI_TEGRA
122 pin_mux_mmc();
123#endif
124
125
126#if defined(CONFIG_DM_VIDEO)
127 pin_mux_display();
128#endif
129
130 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
131
132 power_det_init();
133
134#ifdef CONFIG_SYS_I2C_TEGRA
135# ifdef CONFIG_TEGRA_PMU
136 if (pmu_set_nominal())
137 debug("Failed to select nominal voltages\n");
138# ifdef CONFIG_TEGRA_CLOCK_SCALING
139 err = board_emc_init();
140 if (err)
141 debug("Memory controller init failed: %d\n", err);
142# endif
143# endif
144#endif
145
146#ifdef CONFIG_USB_EHCI_TEGRA
147 pin_mux_usb();
148#endif
149
150#if defined(CONFIG_DM_VIDEO)
151 board_id = tegra_board_id();
152 err = tegra_lcd_pmic_init(board_id);
153 if (err) {
154 debug("Failed to set up LCD PMIC\n");
155 return err;
156 }
157#endif
158
159#ifdef CONFIG_TEGRA_NAND
160 pin_mux_nand();
161#endif
162
163 tegra_xusb_padctl_init();
164
165#ifdef CONFIG_TEGRA_LP0
166
167 warmboot_save_sdram_params();
168
169
170 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
171#endif
172 return nvidia_board_init();
173}
174
175#ifdef CONFIG_BOARD_EARLY_INIT_F
176static void __gpio_early_init(void)
177{
178}
179
180void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
181
182int board_early_init_f(void)
183{
184 if (!clock_early_init_done())
185 clock_early_init();
186
187#if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
188#define USBCMD_FS2 (1 << 15)
189 {
190 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
191 writel(USBCMD_FS2, &usbctlr->usb_cmd);
192 }
193#endif
194
195
196#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
197 if (!tegra_cpu_is_non_secure())
198#endif
199 arch_timer_init();
200
201 pinmux_init();
202 board_init_uart_f();
203
204
205 gpio_early_init();
206 gpio_early_init_uart();
207
208 return 0;
209}
210#endif
211
212int board_late_init(void)
213{
214#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
215 if (tegra_cpu_is_non_secure()) {
216 printf("CPU is in NS mode\n");
217 env_set("cpu_ns_mode", "1");
218 } else {
219 env_set("cpu_ns_mode", "");
220 }
221#endif
222 start_cpu_fan();
223
224 return 0;
225}
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249static ulong carveout_size(void)
250{
251#ifdef CONFIG_ARM64
252 return SZ_512M;
253#else
254 return 0;
255#endif
256}
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262static ulong usable_ram_size_below_4g(void)
263{
264 ulong total_size_below_4g;
265 ulong usable_size_below_4g;
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272 if (gd->ram_size < SZ_2G)
273 total_size_below_4g = gd->ram_size;
274 else
275 total_size_below_4g = SZ_2G;
276
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278 usable_size_below_4g = total_size_below_4g - carveout_size();
279
280 return usable_size_below_4g;
281}
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311int dram_init_banksize(void)
312{
313 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
314 gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
315
316#ifdef CONFIG_PCI
317 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
318#endif
319
320#ifdef CONFIG_PHYS_64BIT
321 if (gd->ram_size > SZ_2G) {
322 gd->bd->bi_dram[1].start = 0x100000000;
323 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
324 } else
325#endif
326 {
327 gd->bd->bi_dram[1].start = 0;
328 gd->bd->bi_dram[1].size = 0;
329 }
330
331 return 0;
332}
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344ulong board_get_usable_ram_top(ulong total_size)
345{
346 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
347}
348