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6
7#include <config.h>
8#include <asm/processor.h>
9#include <asm/macro.h>
10
11#include <asm/processor.h>
12
13 .global lowlevel_init
14
15 .text
16 .align 2
17
18lowlevel_init:
19
20
21 write32 WDTCSR_A, WDTCSR_D
22
23
24 write32 MMUCR_A, MMUCR_D
25
26 write32 FRQCR2_A, FRQCR2_D
27 write32 FRQCR0_A, FRQCR0_D
28
29 write32 CS0CTRL_A, CS0CTRL_D
30 write32 CS1CTRL_A, CS1CTRL_D
31 write32 CS0CTRL2_A, CS0CTRL2_D
32
33 write32 CSPWCR0_A, CSPWCR0_D
34 write32 CSPWCR1_A, CSPWCR1_D
35 write32 CS1GDST_A, CS1GDST_D
36
37
38 mov.l MODEMR, r1
39 mov.l @r1, r0
40 and
41 cmp/eq
42 bt init_lbsc_533
43
44init_lbsc_400:
45
46 write32 CSWCR0_A, CSWCR0_D_400
47 write32 CSWCR1_A, CSWCR1_D
48
49 bra init_dbsc3_400_pad
50 nop
51
52 .align 2
53
54MODEMR: .long 0xFFCC0020
55WDTCSR_A: .long 0xFFCC0004
56WDTCSR_D: .long 0xA5000000
57MMUCR_A: .long 0xFF000010
58MMUCR_D: .long 0x00000004
59
60FRQCR2_A: .long 0xFFC80008
61FRQCR2_D: .long 0x00000000
62FRQCR0_A: .long 0xFFC80000
63FRQCR0_D: .long 0xCF000001
64
65CS0CTRL_A: .long 0xFF800200
66CS0CTRL_D: .long 0x00000020
67CS1CTRL_A: .long 0xFF800204
68CS1CTRL_D: .long 0x00000020
69
70CS0CTRL2_A: .long 0xFF800220
71CS0CTRL2_D: .long 0x00004000
72
73CSPWCR0_A: .long 0xFF800280
74CSPWCR0_D: .long 0x00000000
75CSPWCR1_A: .long 0xFF800284
76CSPWCR1_D: .long 0x00000000
77CS1GDST_A: .long 0xFF8002C0
78CS1GDST_D: .long 0x00000011
79
80init_lbsc_533:
81
82 write32 CSWCR0_A, CSWCR0_D_533
83 write32 CSWCR1_A, CSWCR1_D
84
85 bra init_dbsc3_533_pad
86 nop
87
88 .align 2
89
90CSWCR0_A: .long 0xFF800230
91CSWCR0_D_533: .long 0x01120104
92CSWCR0_D_400: .long 0x02120114
93CSWCR1_A: .long 0xFF800234
94CSWCR1_D: .long 0x077F077F
95
96init_dbsc3_400_pad:
97
98 write32 DBPDCNT3_A, DBPDCNT3_D
99 wait_timer WAIT_200US_400
100
101 write32 DBPDCNT0_A, DBPDCNT0_D_400
102 write32 DBPDCNT3_A, DBPDCNT3_D0
103 write32 DBPDCNT1_A, DBPDCNT1_D
104
105 write32 DBPDCNT3_A, DBPDCNT3_D1
106 wait_timer WAIT_32MCLK
107
108 write32 DBPDCNT3_A, DBPDCNT3_D2
109 wait_timer WAIT_100US_400
110
111 write32 DBPDCNT3_A, DBPDCNT3_D3
112 wait_timer WAIT_16MCLK
113
114 write32 DBPDCNT3_A, DBPDCNT3_D4
115 wait_timer WAIT_200US_400
116
117 write32 DBPDCNT3_A, DBPDCNT3_D5
118 wait_timer WAIT_1MCLK
119
120 write32 DBPDCNT3_A, DBPDCNT3_D6
121 wait_timer WAIT_10KMCLK
122
123 bra init_dbsc3_ctrl_400
124 nop
125
126 .align 2
127
128init_dbsc3_533_pad:
129
130 write32 DBPDCNT3_A, DBPDCNT3_D
131 wait_timer WAIT_200US_533
132
133 write32 DBPDCNT0_A, DBPDCNT0_D_533
134 write32 DBPDCNT3_A, DBPDCNT3_D0
135 write32 DBPDCNT1_A, DBPDCNT1_D
136
137 write32 DBPDCNT3_A, DBPDCNT3_D1
138 wait_timer WAIT_32MCLK
139
140 write32 DBPDCNT3_A, DBPDCNT3_D2
141 wait_timer WAIT_100US_533
142
143 write32 DBPDCNT3_A, DBPDCNT3_D3
144 wait_timer WAIT_16MCLK
145
146 write32 DBPDCNT3_A, DBPDCNT3_D4
147 wait_timer WAIT_200US_533
148
149 write32 DBPDCNT3_A, DBPDCNT3_D5
150 wait_timer WAIT_1MCLK
151
152 write32 DBPDCNT3_A, DBPDCNT3_D6
153 wait_timer WAIT_10KMCLK
154
155 bra init_dbsc3_ctrl_533
156 nop
157
158 .align 2
159
160WAIT_200US_400: .long 40000
161WAIT_200US_533: .long 53300
162WAIT_100US_400: .long 20000
163WAIT_100US_533: .long 26650
164WAIT_32MCLK: .long 32
165WAIT_16MCLK: .long 16
166WAIT_1MCLK: .long 1
167WAIT_10KMCLK: .long 10000
168
169DBPDCNT0_A: .long 0xFE800200
170DBPDCNT0_D_533: .long 0x00010245
171DBPDCNT0_D_400: .long 0x00010235
172DBPDCNT1_A: .long 0xFE800204
173DBPDCNT1_D: .long 0x00000014
174DBPDCNT3_A: .long 0xFE80020C
175DBPDCNT3_D: .long 0x80000000
176DBPDCNT3_D0: .long 0x800F0000
177DBPDCNT3_D1: .long 0x800F1000
178DBPDCNT3_D2: .long 0x820F1000
179DBPDCNT3_D3: .long 0x860F1000
180DBPDCNT3_D4: .long 0x870F1000
181DBPDCNT3_D5: .long 0x870F3000
182DBPDCNT3_D6: .long 0x870F7000
183
184init_dbsc3_ctrl_400:
185
186 write32 DBKIND_A, DBKIND_D
187 write32 DBCONF_A, DBCONF_D
188
189 write32 DBTR0_A, DBTR0_D_400
190 write32 DBTR1_A, DBTR1_D_400
191 write32 DBTR2_A, DBTR2_D
192 write32 DBTR3_A, DBTR3_D_400
193 write32 DBTR4_A, DBTR4_D_400
194 write32 DBTR5_A, DBTR5_D_400
195 write32 DBTR6_A, DBTR6_D_400
196 write32 DBTR7_A, DBTR7_D
197 write32 DBTR8_A, DBTR8_D_400
198 write32 DBTR9_A, DBTR9_D
199 write32 DBTR10_A, DBTR10_D_400
200 write32 DBTR11_A, DBTR11_D
201 write32 DBTR12_A, DBTR12_D_400
202 write32 DBTR13_A, DBTR13_D_400
203 write32 DBTR14_A, DBTR14_D
204 write32 DBTR15_A, DBTR15_D
205 write32 DBTR16_A, DBTR16_D_400
206 write32 DBTR17_A, DBTR17_D_400
207 write32 DBTR18_A, DBTR18_D_400
208
209 write32 DBBL_A, DBBL_D
210 write32 DBRNK0_A, DBRNK0_D
211
212 write32 DBCMD_A, DBCMD_D0_400
213 write32 DBCMD_A, DBCMD_D1
214 write32 DBCMD_A, DBCMD_D2
215 write32 DBCMD_A, DBCMD_D3
216 write32 DBCMD_A, DBCMD_D4
217 write32 DBCMD_A, DBCMD_D5_400
218 write32 DBCMD_A, DBCMD_D6
219 write32 DBCMD_A, DBCMD_D7
220 write32 DBCMD_A, DBCMD_D8
221 write32 DBCMD_A, DBCMD_D9_400
222 write32 DBCMD_A, DBCMD_D10
223 write32 DBCMD_A, DBCMD_D11
224 write32 DBCMD_A, DBCMD_D12
225
226 write32 DBRFCNF0_A, DBRFCNF0_D
227 write32 DBRFCNF1_A, DBRFCNF1_D_400
228 write32 DBRFCNF2_A, DBRFCNF2_D
229 write32 DBRFEN_A, DBRFEN_D
230 write32 DBACEN_A, DBACEN_D
231 write32 DBACEN_A, DBACEN_D
232
233
234 mov.l DBWAIT_A, r1
235 synco
236 mov.l @r1, r0
237 synco
238
239
240 mov.l SDRAM_A, r1
241 synco
242 mov.l @r1, r0
243 synco
244
245
246
247 bra finish_init_sh7734
248 nop
249
250 .align 2
251
252init_dbsc3_ctrl_533:
253
254 write32 DBKIND_A, DBKIND_D
255 write32 DBCONF_A, DBCONF_D
256
257 write32 DBTR0_A, DBTR0_D_533
258 write32 DBTR1_A, DBTR1_D_533
259 write32 DBTR2_A, DBTR2_D
260 write32 DBTR3_A, DBTR3_D_533
261 write32 DBTR4_A, DBTR4_D_533
262 write32 DBTR5_A, DBTR5_D_533
263 write32 DBTR6_A, DBTR6_D_533
264 write32 DBTR7_A, DBTR7_D
265 write32 DBTR8_A, DBTR8_D_533
266 write32 DBTR9_A, DBTR9_D
267 write32 DBTR10_A, DBTR10_D_533
268 write32 DBTR11_A, DBTR11_D
269 write32 DBTR12_A, DBTR12_D_533
270 write32 DBTR13_A, DBTR13_D_533
271 write32 DBTR14_A, DBTR14_D
272 write32 DBTR15_A, DBTR15_D
273 write32 DBTR16_A, DBTR16_D_533
274 write32 DBTR17_A, DBTR17_D_533
275 write32 DBTR18_A, DBTR18_D_533
276
277 write32 DBBL_A, DBBL_D
278 write32 DBRNK0_A, DBRNK0_D
279
280 write32 DBCMD_A, DBCMD_D0_533
281 write32 DBCMD_A, DBCMD_D1
282 write32 DBCMD_A, DBCMD_D2
283 write32 DBCMD_A, DBCMD_D3
284 write32 DBCMD_A, DBCMD_D4
285 write32 DBCMD_A, DBCMD_D5_533
286 write32 DBCMD_A, DBCMD_D6
287 write32 DBCMD_A, DBCMD_D7
288 write32 DBCMD_A, DBCMD_D8
289 write32 DBCMD_A, DBCMD_D9_533
290 write32 DBCMD_A, DBCMD_D10
291 write32 DBCMD_A, DBCMD_D11
292 write32 DBCMD_A, DBCMD_D12
293
294 write32 DBRFCNF0_A, DBRFCNF0_D
295 write32 DBRFCNF1_A, DBRFCNF1_D_533
296 write32 DBRFCNF2_A, DBRFCNF2_D
297 write32 DBRFEN_A, DBRFEN_D
298 write32 DBACEN_A, DBACEN_D
299 write32 DBACEN_A, DBACEN_D
300
301
302 mov.l DBWAIT_A, r1
303 synco
304 mov.l @r1, r0
305 synco
306
307
308 mov.l SDRAM_A, r1
309 synco
310 mov.l @r1, r0
311 synco
312
313
314
315 bra finish_init_sh7734
316 nop
317
318 .align 2
319
320DBKIND_A: .long 0xFE800020
321DBKIND_D: .long 0x00000005
322DBCONF_A: .long 0xFE800024
323DBCONF_D: .long 0x0D020A01
324
325DBTR0_A: .long 0xFE800040
326DBTR0_D_533:.long 0x00000004
327DBTR0_D_400:.long 0x00000003
328DBTR1_A: .long 0xFE800044
329DBTR1_D_533:.long 0x00000003
330DBTR1_D_400:.long 0x00000002
331DBTR2_A: .long 0xFE800048
332DBTR2_D: .long 0x00000000
333DBTR3_A: .long 0xFE800050
334DBTR3_D_533:.long 0x00000004
335DBTR3_D_400:.long 0x00000003
336
337DBTR4_A: .long 0xFE800054
338DBTR4_D_533:.long 0x00050004
339DBTR4_D_400:.long 0x00050003
340
341DBTR5_A: .long 0xFE800058
342DBTR5_D_533:.long 0x0000000F
343DBTR5_D_400:.long 0x0000000B
344
345DBTR6_A: .long 0xFE80005C
346DBTR6_D_533:.long 0x0000000B
347DBTR6_D_400:.long 0x00000008
348
349DBTR7_A: .long 0xFE800060
350DBTR7_D: .long 0x00000002
351
352DBTR8_A: .long 0xFE800064
353DBTR8_D_533:.long 0x0000000D
354DBTR8_D_400:.long 0x0000000A
355
356DBTR9_A: .long 0xFE800068
357DBTR9_D: .long 0x00000002
358
359DBTR10_A: .long 0xFE80006C
360DBTR10_D_533:.long 0x00000004
361DBTR10_D_400:.long 0x00000003
362
363DBTR11_A: .long 0xFE800070
364DBTR11_D: .long 0x00000008
365
366DBTR12_A: .long 0xFE800074
367DBTR12_D_533:.long 0x00000009
368DBTR12_D_400:.long 0x00000008
369
370DBTR13_A: .long 0xFE800078
371DBTR13_D_533:.long 0x00000022
372DBTR13_D_400:.long 0x0000001A
373
374DBTR14_A: .long 0xFE80007C
375DBTR14_D: .long 0x00070002
376
377DBTR15_A: .long 0xFE800080
378DBTR15_D: .long 0x00000003
379
380DBTR16_A: .long 0xFE800084
381DBTR16_D_533:.long 0x120A1001
382DBTR16_D_400:.long 0x12091001
383
384DBTR17_A: .long 0xFE800088
385DBTR17_D_533:.long 0x00040000
386DBTR17_D_400:.long 0x00030000
387
388DBTR18_A: .long 0xFE80008C
389DBTR18_D_533:.long 0x02010200
390DBTR18_D_400:.long 0x02000207
391
392DBBL_A: .long 0xFE8000B0
393DBBL_D: .long 0x00000000
394
395DBRNK0_A: .long 0xFE800100
396DBRNK0_D: .long 0x00000001
397
398DBCMD_A: .long 0xFE800018
399DBCMD_D0_533: .long 0x1100006B
400DBCMD_D0_400: .long 0x11000050
401DBCMD_D1: .long 0x0B000000
402DBCMD_D2: .long 0x2A004000
403DBCMD_D3: .long 0x2B006000
404DBCMD_D4: .long 0x29002044
405DBCMD_D5_533: .long 0x28000743
406DBCMD_D5_400: .long 0x28000533
407DBCMD_D6: .long 0x0B000000
408DBCMD_D7: .long 0x0C000000
409DBCMD_D8: .long 0x0C000000
410DBCMD_D9_533: .long 0x28000643
411DBCMD_D9_400: .long 0x28000433
412DBCMD_D10: .long 0x000000C8
413DBCMD_D11: .long 0x290023C4
414DBCMD_D12: .long 0x29002004
415
416DBRFCNF0_A: .long 0xFE8000E0
417DBRFCNF0_D: .long 0x000001FF
418DBRFCNF1_A: .long 0xFE8000E4
419DBRFCNF1_D_533: .long 0x00000805
420DBRFCNF1_D_400: .long 0x00000618
421
422DBRFCNF2_A: .long 0xFE8000E8
423DBRFCNF2_D: .long 0x00000000
424
425DBRFEN_A: .long 0xFE800014
426DBRFEN_D: .long 0x00000001
427
428DBACEN_A: .long 0xFE800010
429DBACEN_D: .long 0x00000001
430
431DBWAIT_A: .long 0xFE80001C
432SDRAM_A: .long 0x0C000000
433
434finish_init_sh7734:
435 write32 CCR_A, CCR_D
436
437 stc sr, r0
438 mov.l SR_MASK_D, r1
439 and r1, r0
440 ldc r0, sr
441
442 rts
443 nop
444
445 .align 2
446
447CCR_A: .long 0xFF00001C
448CCR_D: .long 0x0000090B
449SR_MASK_D: .long 0xEFFFFF0F
450
