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23#include <common.h>
24#include <malloc.h>
25#include <asm/processor.h>
26#include <asm/mach-types.h>
27#include <asm/io.h>
28#include <asm/arch/sys_proto.h>
29#include <asm/gpio.h>
30#include <asm/arch/rmobile.h>
31
32#define s_init_wait(cnt) \
33 ({ \
34 volatile u32 i = 0x10000 * cnt; \
35 while (i > 0) \
36 i--; \
37 })
38
39#define USBCR1 0xE605810A
40
41void s_init(void)
42{
43 struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
44 struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
45 struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
46 struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
47 struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
48 struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
49
50
51 writew(0xA500, &rwdt0->rwtcsra0);
52 writew(0xA500, &rwdt1->rwtcsra0);
53
54
55 writel(0xFF800080, &cpg->rmstpcr4);
56 writel(0xFF800080, &cpg->smstpcr4);
57
58
59 writel(0x00000080, &cpg->usbckcr);
60 s_init_wait(1);
61
62
63 writew(0x0710, USBCR1);
64
65
66 writel(0x00000000, &cpg->frqcrb);
67 writel(0x62030533, &cpg->frqcra);
68 writel(0x208A354E, &cpg->frqcrc);
69 writel(0x80331050, &cpg->frqcrb);
70 s_init_wait(1);
71
72 writel(0x00000000, &cpg->frqcrd);
73 s_init_wait(1);
74
75
76 writel(0x0000010B, &cpg->subckcr);
77
78
79 writel(0x00004004, &cpg->pllc01cr);
80 s_init_wait(1);
81
82 writel(0xa0000000, &cpg->pllc2cr);
83 s_init_wait(2);
84
85
86 writel(0x0000001B, &bsc->cmncr);
87
88 writel(0x20000000, &dbsc->dbcmd);
89 writel(0x10009C40, &dbsc->dbcmd);
90 s_init_wait(1);
91
92 writel(0x00000007, &dbsc->dbkind);
93 writel(0x0E030A02, &dbsc->dbconf0);
94 writel(0x00000001, &dbsc->dbphytype);
95 writel(0x00000000, &dbsc->dbbl);
96 writel(0x00000006, &dbsc->dbtr0);
97 writel(0x00000005, &dbsc->dbtr1);
98 writel(0x00000000, &dbsc->dbtr2);
99 writel(0x00000006, &dbsc->dbtr3);
100 writel(0x00080006, &dbsc->dbtr4);
101 writel(0x00000015, &dbsc->dbtr5);
102 writel(0x0000000f, &dbsc->dbtr6);
103 writel(0x00000004, &dbsc->dbtr7);
104 writel(0x00000018, &dbsc->dbtr8);
105 writel(0x00000006, &dbsc->dbtr9);
106 writel(0x00000006, &dbsc->dbtr10);
107 writel(0x0000000F, &dbsc->dbtr11);
108 writel(0x0000000D, &dbsc->dbtr12);
109 writel(0x000000A0, &dbsc->dbtr13);
110 writel(0x000A0003, &dbsc->dbtr14);
111 writel(0x00000003, &dbsc->dbtr15);
112 writel(0x40005005, &dbsc->dbtr16);
113 writel(0x0C0C0000, &dbsc->dbtr17);
114 writel(0x00000200, &dbsc->dbtr18);
115 writel(0x00000040, &dbsc->dbtr19);
116 writel(0x00000001, &dbsc->dbrnk0);
117 writel(0x00000110, &dbsc->dbdficnt);
118 writel(0x00000101, &ddrp->funcctrl);
119 writel(0x00000001, &ddrp->dllctrl);
120 writel(0x00000186, &ddrp->zqcalctrl);
121 writel(0xB3440051, &ddrp->zqodtctrl);
122 writel(0x94449443, &ddrp->rdctrl);
123 writel(0x000000C0, &ddrp->rdtmg);
124 writel(0x00000101, &ddrp->fifoinit);
125 writel(0x02060506, &ddrp->outctrl);
126 writel(0x00004646, &ddrp->dqcalofs1);
127 writel(0x00004646, &ddrp->dqcalofs2);
128 writel(0x800000aa, &ddrp->dqcalexp);
129 writel(0x00000000, &ddrp->dllctrl);
130 writel(0x00000000, DDRPNCNT);
131
132 writel(0x0000000C, &dbsc->dbcmd);
133 readl(&dbsc->dbwait);
134 s_init_wait(1);
135
136 writel(0x00000002, DDRPNCNT);
137
138 writel(0x0000000C, &dbsc->dbcmd);
139 readl(&dbsc->dbwait);
140 s_init_wait(1);
141
142 writel(0x00000187, &ddrp->zqcalctrl);
143
144 writel(0x00009C40, &dbsc->dbcmd);
145 readl(&dbsc->dbwait);
146 s_init_wait(1);
147
148 writel(0x00009C40, &dbsc->dbcmd);
149 readl(&dbsc->dbwait);
150 s_init_wait(1);
151
152 writel(0x00000010, &dbsc->dbdficnt);
153 writel(0x02060507, &ddrp->outctrl);
154
155 writel(0x00009C40, &dbsc->dbcmd);
156 readl(&dbsc->dbwait);
157 s_init_wait(1);
158
159 writel(0x21009C40, &dbsc->dbcmd);
160 readl(&dbsc->dbwait);
161 s_init_wait(1);
162
163 writel(0x00009C40, &dbsc->dbcmd);
164 readl(&dbsc->dbwait);
165 s_init_wait(1);
166
167 writel(0x00009C40, &dbsc->dbcmd);
168 readl(&dbsc->dbwait);
169 s_init_wait(1);
170
171 writel(0x00009C40, &dbsc->dbcmd);
172 readl(&dbsc->dbwait);
173 s_init_wait(1);
174
175 writel(0x00009C40, &dbsc->dbcmd);
176 readl(&dbsc->dbwait);
177 s_init_wait(1);
178
179 writel(0x11000044, &dbsc->dbcmd);
180 readl(&dbsc->dbwait);
181 s_init_wait(1);
182
183 writel(0x2A000000, &dbsc->dbcmd);
184 readl(&dbsc->dbwait);
185 s_init_wait(1);
186
187 writel(0x2B000000, &dbsc->dbcmd);
188 readl(&dbsc->dbwait);
189
190 writel(0x29000004, &dbsc->dbcmd);
191 readl(&dbsc->dbwait);
192
193 writel(0x28001520, &dbsc->dbcmd);
194 readl(&dbsc->dbwait);
195 s_init_wait(1);
196
197 writel(0x03000200, &dbsc->dbcmd);
198 readl(&dbsc->dbwait);
199 s_init_wait(1);
200
201 writel(0x000001FF, &dbsc->dbrfcnf0);
202 writel(0x00010C30, &dbsc->dbrfcnf1);
203 writel(0x00000000, &dbsc->dbrfcnf2);
204
205 writel(0x00000001, &dbsc->dbrfen);
206 writel(0x00000001, &dbsc->dbacen);
207
208
209 writel(0x00410400, &bsc->cs0bcr);
210 writel(0x00410400, &bsc->cs2bcr);
211 writel(0x00410400, &bsc->cs5bbcr);
212 writel(0x02CB0400, &bsc->cs6abcr);
213
214 writel(0x00000440, &bsc->cs0wcr);
215 writel(0x00000440, &bsc->cs2wcr);
216 writel(0x00000240, &bsc->cs5bwcr);
217 writel(0x00000240, &bsc->cs6awcr);
218
219 writel(0x00000005, &bsc->rbwtcnt);
220 writel(0x00000002, &bsc->cs0wcr2);
221 writel(0x00000002, &bsc->cs2wcr2);
222 writel(0x00000002, &bsc->cs4wcr2);
223}
224
225#define GPIO_ICCR (0xE60581A0)
226#define ICCR_15BIT (1 << 15)
227#define IIC0_CONTA (1 << 7)
228#define IIC0_CONTB (1 << 6)
229#define IIC1_CONTA (1 << 5)
230#define IIC1_CONTB (1 << 4)
231#define IIC0_PS33E (1 << 1)
232#define IIC1_PS33E (1 << 0)
233#define GPIO_ICCR_DATA \
234 (ICCR_15BIT | \
235 IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \
236 IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
237
238#define MSTPCR1 0xE6150134
239#define TMU0_MSTP125 (1 << 25)
240#define I2C0_MSTP116 (1 << 16)
241
242#define MSTPCR3 0xE615013C
243#define I2C1_MSTP323 (1 << 23)
244#define GETHER_MSTP309 (1 << 9)
245
246#define GPIO_SCIFA1_TXD (0xE60520C4)
247#define GPIO_SCIFA1_RXD (0xE60520C3)
248
249int board_early_init_f(void)
250{
251
252 clrbits_le32(MSTPCR1, TMU0_MSTP125);
253
254
255 clrbits_le32(MSTPCR3, GETHER_MSTP309);
256
257
258 clrbits_le32(MSTPCR1, I2C0_MSTP116);
259 clrbits_le32(MSTPCR3, I2C1_MSTP323);
260
261
262 writeb(1, GPIO_SCIFA1_TXD);
263 writeb(1, GPIO_SCIFA1_RXD);
264
265
266 writew(GPIO_ICCR_DATA, GPIO_ICCR);
267
268 return 0;
269}
270
271DECLARE_GLOBAL_DATA_PTR;
272int board_init(void)
273{
274
275 gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO800EVA;
276
277 gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
278
279
280 r8a7740_pinmux_init();
281
282
283 gpio_request(GPIO_FN_ET_CRS, NULL);
284 gpio_request(GPIO_FN_ET_MDC, NULL);
285 gpio_request(GPIO_FN_ET_MDIO, NULL);
286 gpio_request(GPIO_FN_ET_TX_ER, NULL);
287 gpio_request(GPIO_FN_ET_RX_ER, NULL);
288 gpio_request(GPIO_FN_ET_ERXD0, NULL);
289 gpio_request(GPIO_FN_ET_ERXD1, NULL);
290 gpio_request(GPIO_FN_ET_ERXD2, NULL);
291 gpio_request(GPIO_FN_ET_ERXD3, NULL);
292 gpio_request(GPIO_FN_ET_TX_CLK, NULL);
293 gpio_request(GPIO_FN_ET_TX_EN, NULL);
294 gpio_request(GPIO_FN_ET_ETXD0, NULL);
295 gpio_request(GPIO_FN_ET_ETXD1, NULL);
296 gpio_request(GPIO_FN_ET_ETXD2, NULL);
297 gpio_request(GPIO_FN_ET_ETXD3, NULL);
298 gpio_request(GPIO_FN_ET_PHY_INT, NULL);
299 gpio_request(GPIO_FN_ET_COL, NULL);
300 gpio_request(GPIO_FN_ET_RX_DV, NULL);
301 gpio_request(GPIO_FN_ET_RX_CLK, NULL);
302
303 gpio_request(GPIO_PORT18, NULL);
304 gpio_direction_output(GPIO_PORT18, 1);
305
306 return 0;
307}
308
309int dram_init(void)
310{
311 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
312 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
313
314 return 0;
315}
316
317const struct rmobile_sysinfo sysinfo = {
318 CONFIG_ARCH_RMOBILE_BOARD_STRING
319};
320
321int board_late_init(void)
322{
323 return 0;
324}
325
326void reset_cpu(ulong addr)
327{
328}
329
