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7#include <common.h>
8#include <asm/mmu.h>
9#include <asm/immap_85xx.h>
10#include <asm/processor.h>
11#include <fsl_ddr_sdram.h>
12#include <fsl_ddr_dimm_params.h>
13#include <asm/io.h>
14#include <asm/fsl_law.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18#ifndef CONFIG_SYS_DDR_RAW_TIMING
19#define CONFIG_SYS_DRAM_SIZE 1024
20
21fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
22 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
23 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
24 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
25 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
26 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
27 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
28 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
29 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
30 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
31 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
32 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
33 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
34 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
35 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
36 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
37 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
38 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
39 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
40 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
41 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
42 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
43 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
44 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
45 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
46};
47
48fixed_ddr_parm_t fixed_ddr_parm_0[] = {
49 {750, 850, &ddr_cfg_regs_800},
50 {0, 0, NULL}
51};
52
53unsigned long get_sdram_size(void)
54{
55 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
56}
57
58
59
60
61phys_size_t fixed_sdram(void)
62{
63 int i;
64 char buf[32];
65 fsl_ddr_cfg_regs_t ddr_cfg_regs;
66 phys_size_t ddr_size;
67 ulong ddr_freq, ddr_freq_mhz;
68
69 ddr_freq = get_ddr_freq(0);
70 ddr_freq_mhz = ddr_freq / 1000000;
71
72 printf("Configuring DDR for %s MT/s data rate\n",
73 strmhz(buf, ddr_freq));
74
75 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
76 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
77 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
78 memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
79 sizeof(ddr_cfg_regs));
80 break;
81 }
82 }
83
84 if (fixed_ddr_parm_0[i].max_freq == 0) {
85 panic("Unsupported DDR data rate %s MT/s data rate\n",
86 strmhz(buf, ddr_freq));
87 }
88
89 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
90 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
91
92 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
93 LAW_TRGT_IF_DDR_1) < 0) {
94 printf("ERROR setting Local Access Windows for DDR\n");
95 return 0;
96 }
97
98 return ddr_size;
99}
100
101#else
102
103dimm_params_t ddr_raw_timing = {
104 .n_ranks = 1,
105 .rank_density = 1073741824u,
106 .capacity = 1073741824u,
107 .primary_sdram_width = 32,
108 .ec_sdram_width = 0,
109 .registered_dimm = 0,
110 .mirrored_dimm = 0,
111 .n_row_addr = 15,
112 .n_col_addr = 10,
113 .n_banks_per_sdram_device = 8,
114 .edc_config = 0,
115 .burst_lengths_bitmask = 0x0c,
116
117 .tckmin_x_ps = 1870,
118 .caslat_x = 0x1e << 4,
119 .taa_ps = 13125,
120 .twr_ps = 15000,
121 .trcd_ps = 13125,
122 .trrd_ps = 7500,
123 .trp_ps = 13125,
124 .tras_ps = 37500,
125 .trc_ps = 50625,
126 .trfc_ps = 160000,
127 .twtr_ps = 7500,
128 .trtp_ps = 7500,
129 .refresh_rate_ps = 7800000,
130 .tfaw_ps = 37500,
131};
132
133int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
134 unsigned int controller_number,
135 unsigned int dimm_number)
136{
137 const char dimm_model[] = "Fixed DDR on board";
138
139 if ((controller_number == 0) && (dimm_number == 0)) {
140 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
141 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
142 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
143 }
144
145 return 0;
146}
147
148void fsl_ddr_board_options(memctl_options_t *popts,
149 dimm_params_t *pdimm,
150 unsigned int ctrl_num)
151{
152 int i;
153 popts->clk_adjust = 6;
154 popts->cpo_override = 0x1f;
155 popts->write_data_delay = 2;
156 popts->half_strength_driver_enable = 1;
157
158 popts->wrlvl_en = 1;
159 popts->wrlvl_override = 1;
160 popts->wrlvl_sample = 0xf;
161 popts->wrlvl_start = 0x8;
162 popts->trwt_override = 1;
163 popts->trwt = 0;
164
165 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
166 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
167 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
168 }
169}
170
171#endif
172
