LXR uboot/board/freescale/mpc8349itx/pci.c

   1/*
   2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8
   9#include <asm/mmu.h>
  10#include <asm/io.h>
  11#include <mpc83xx.h>
  12#include <pci.h>
  13#include <i2c.h>
  14#include <asm/fsl_i2c.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18static struct pci_region pci1_regions[] = {
  19        {
  20                bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  21                phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  22                size: CONFIG_SYS_PCI1_MEM_SIZE,
  23                flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  24        },
  25        {
  26                bus_start: CONFIG_SYS_PCI1_IO_BASE,
  27                phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  28                size: CONFIG_SYS_PCI1_IO_SIZE,
  29                flags: PCI_REGION_IO
  30        },
  31        {
  32                bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  33                phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  34                size: CONFIG_SYS_PCI1_MMIO_SIZE,
  35                flags: PCI_REGION_MEM
  36        },
  37};
  38
  39#ifdef CONFIG_MPC83XX_PCI2
  40static struct pci_region pci2_regions[] = {
  41        {
  42                bus_start: CONFIG_SYS_PCI2_MEM_BASE,
  43                phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
  44                size: CONFIG_SYS_PCI2_MEM_SIZE,
  45                flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  46        },
  47        {
  48                bus_start: CONFIG_SYS_PCI2_IO_BASE,
  49                phys_start: CONFIG_SYS_PCI2_IO_PHYS,
  50                size: CONFIG_SYS_PCI2_IO_SIZE,
  51                flags: PCI_REGION_IO
  52        },
  53        {
  54                bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
  55                phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
  56                size: CONFIG_SYS_PCI2_MMIO_SIZE,
  57                flags: PCI_REGION_MEM
  58        },
  59};
  60#endif
  61
  62void pci_init_board(void)
  63{
  64        volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  65        volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  66        volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  67#ifndef CONFIG_MPC83XX_PCI2
  68        struct pci_region *reg[] = { pci1_regions };
  69#else
  70        struct pci_region *reg[] = { pci1_regions, pci2_regions };
  71#endif
  72        u8 reg8;
  73
  74#if defined(CONFIG_SYS_I2C)
  75        i2c_set_bus_num(1);
  76        /* Read the PCI_M66EN jumper setting */
  77        if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
  78            (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
  79                if (reg8 & I2C_8574_PCI66)
  80                        clk->occr = 0xff000000; /* 66 MHz PCI */
  81                else
  82                        clk->occr = 0xff600001; /* 33 MHz PCI */
  83        } else {
  84                clk->occr = 0xff600001; /* 33 MHz PCI */
  85        }
  86#else
  87        clk->occr = 0xff000000; /* 66 MHz PCI */
  88#endif
  89        udelay(2000);
  90
  91        /* Configure PCI Local Access Windows */
  92        pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
  93        pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
  94
  95        pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
  96        pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
  97
  98        udelay(2000);
  99
 100#ifndef CONFIG_MPC83XX_PCI2
 101        mpc83xx_pci_init(1, reg);
 102#else
 103        mpc83xx_pci_init(2, reg);
 104#endif
 105}
 106