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9#include <common.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/crm_regs.h>
12#include <asm/arch/iomux.h>
13#include <asm/arch/mx6-pins.h>
14#include <asm/arch/mxc_hdmi.h>
15#include <asm/arch/sys_proto.h>
16#include <asm/gpio.h>
17#include <asm/mach-imx/boot_mode.h>
18#include <asm/mach-imx/sata.h>
19#include <asm/mach-imx/spi.h>
20#include <asm/mach-imx/video.h>
21#include <asm/io.h>
22#include <asm/setup.h>
23#include <dm.h>
24#include <dm/platform_data/serial_mxc.h>
25#include <hwconfig.h>
26#include <i2c.h>
27#include <fdt_support.h>
28#include <fsl_esdhc.h>
29#include <jffs2/load_kernel.h>
30#include <linux/ctype.h>
31#include <miiphy.h>
32#include <mtd_node.h>
33#include <netdev.h>
34#include <pci.h>
35#include <power/pmic.h>
36#include <power/ltc3676_pmic.h>
37#include <power/pfuze100_pmic.h>
38#include <fdt_support.h>
39#include <jffs2/load_kernel.h>
40#include <spi_flash.h>
41
42#include "gsc.h"
43#include "common.h"
44
45DECLARE_GLOBAL_DATA_PTR;
46
47
48
49
50
51
52struct ventana_board_info ventana_info;
53
54static int board_type;
55
56
57static iomux_v3_cfg_t const enet_pads[] = {
58 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
59 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
60 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
61 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
62 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
63 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
64 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
65 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
66 MUX_PAD_CTRL(ENET_PAD_CTRL)),
67 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
68 MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
75 MUX_PAD_CTRL(ENET_PAD_CTRL)),
76
77 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
78};
79
80#ifdef CONFIG_CMD_NAND
81static iomux_v3_cfg_t const nfc_pads[] = {
82 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
83 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
84 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
85 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
86 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
87 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
88 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
89 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
90 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
91 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
92 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
95 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
96 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
97};
98
99static void setup_gpmi_nand(void)
100{
101 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
102
103
104 SETUP_IOMUX_PADS(nfc_pads);
105
106
107 clrsetbits_le32(&mxc_ccm->cs2cdr,
108 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
109 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
110 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
111 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
112 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
113 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
114
115
116 setbits_le32(&mxc_ccm->CCGR4,
117 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
118 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
119 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
120 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
121 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
122
123
124 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
125}
126#endif
127
128static void setup_iomux_enet(int gpio)
129{
130 SETUP_IOMUX_PADS(enet_pads);
131
132
133 gpio_request(gpio, "phy_rst#");
134 gpio_direction_output(gpio, 0);
135 mdelay(10);
136 gpio_set_value(gpio, 1);
137 mdelay(100);
138}
139
140#ifdef CONFIG_USB_EHCI_MX6
141static iomux_v3_cfg_t const usb_pads[] = {
142 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
143 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
144
145 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
146};
147
148int board_ehci_hcd_init(int port)
149{
150 int gpio;
151
152 SETUP_IOMUX_PADS(usb_pads);
153
154
155 switch (board_type) {
156 case GW53xx:
157 case GW552x:
158 gpio = (IMX_GPIO_NR(1, 9));
159 break;
160 case GW54proto:
161 case GW54xx:
162 gpio = (IMX_GPIO_NR(1, 16));
163 break;
164 default:
165 return 0;
166 }
167
168
169 gpio_request(gpio, "usb_hub_rst#");
170 gpio_direction_output(gpio, 0);
171 mdelay(2);
172 gpio_set_value(gpio, 1);
173
174 return 0;
175}
176
177int board_ehci_power(int port, int on)
178{
179
180 if (!port && board_type < GW_UNKNOWN) {
181 if (gpio_cfg[board_type].otgpwr_en)
182 gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
183 }
184 return 0;
185}
186#endif
187
188#ifdef CONFIG_MXC_SPI
189iomux_v3_cfg_t const ecspi1_pads[] = {
190
191 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
192 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
193 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
194 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
195};
196
197int board_spi_cs_gpio(unsigned bus, unsigned cs)
198{
199 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
200}
201
202static void setup_spi(void)
203{
204 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
205 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
206 SETUP_IOMUX_PADS(ecspi1_pads);
207}
208#endif
209
210
211int board_phy_config(struct phy_device *phydev)
212{
213 unsigned short val;
214
215
216 if (phydev->phy_id == 0x1410dd1) {
217
218
219
220
221
222 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
223 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
224 val &= 0xff00;
225 val |= 0x0017;
226 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
227 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
228 }
229
230
231 else if (phydev->phy_id == 0x2000a231) {
232
233 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
234 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
235 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
236 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
237 val &= ~0x1f00;
238 val |= 0x0b00;
239 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
240 }
241
242 if (phydev->drv->config)
243 phydev->drv->config(phydev);
244
245 return 0;
246}
247
248#ifdef CONFIG_MV88E61XX_SWITCH
249int mv88e61xx_hw_reset(struct phy_device *phydev)
250{
251 struct mii_dev *bus = phydev->bus;
252
253
254 debug("enabling RGMII_REFCLK\n");
255 bus->write(bus, 0x1c , 0,
256 0x1a ,
257 (1 << 15) | (0x62 << 8) | 0xfe);
258 bus->write(bus, 0x1c , 0,
259 0x1a ,
260 (1 << 15) | (0x68 << 8) | 7);
261
262
263 debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
264
265 bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
266 phydev->autoneg = AUTONEG_DISABLE;
267 phydev->speed = SPEED_1000;
268 phydev->duplex = DUPLEX_FULL;
269
270
271 bus->write(bus, 0x10, 0, 0x16, 0x8089);
272 bus->write(bus, 0x11, 0, 0x16, 0x8089);
273 bus->write(bus, 0x12, 0, 0x16, 0x8089);
274 bus->write(bus, 0x13, 0, 0x16, 0x8089);
275
276 return 0;
277}
278#endif
279
280int board_eth_init(bd_t *bis)
281{
282#ifdef CONFIG_FEC_MXC
283 struct ventana_board_info *info = &ventana_info;
284
285 if (test_bit(EECONFIG_ETH0, info->config)) {
286 setup_iomux_enet(GP_PHY_RST);
287 cpu_eth_init(bis);
288 }
289#endif
290
291#ifdef CONFIG_E1000
292 e1000_initialize(bis);
293#endif
294
295#ifdef CONFIG_CI_UDC
296
297 usb_eth_initialize(bis);
298#endif
299
300
301 if (!env_get("ethprime")) {
302 struct eth_device *dev = eth_get_dev_by_index(0);
303 if (dev) {
304 env_set("ethprime", dev->name);
305 printf("set ethprime to %s\n", env_get("ethprime"));
306 }
307 }
308
309 return 0;
310}
311
312#if defined(CONFIG_VIDEO_IPUV3)
313
314static void enable_hdmi(struct display_info_t const *dev)
315{
316 imx_enable_hdmi_phy();
317}
318
319static int detect_i2c(struct display_info_t const *dev)
320{
321 return i2c_set_bus_num(dev->bus) == 0 &&
322 i2c_probe(dev->addr) == 0;
323}
324
325static void enable_lvds(struct display_info_t const *dev)
326{
327 struct iomuxc *iomux = (struct iomuxc *)
328 IOMUXC_BASE_ADDR;
329
330
331 u32 reg = readl(&iomux->gpr[2]);
332 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
333 writel(reg, &iomux->gpr[2]);
334
335
336 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
337 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
338 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
339 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
340 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
341}
342
343struct display_info_t const displays[] = {{
344
345 .bus = -1,
346 .addr = 0,
347 .pixfmt = IPU_PIX_FMT_RGB24,
348 .detect = detect_hdmi,
349 .enable = enable_hdmi,
350 .mode = {
351 .name = "HDMI",
352 .refresh = 60,
353 .xres = 1024,
354 .yres = 768,
355 .pixclock = 15385,
356 .left_margin = 220,
357 .right_margin = 40,
358 .upper_margin = 21,
359 .lower_margin = 7,
360 .hsync_len = 60,
361 .vsync_len = 10,
362 .sync = FB_SYNC_EXT,
363 .vmode = FB_VMODE_NONINTERLACED
364} }, {
365
366 .bus = 2,
367 .addr = 0x4,
368 .pixfmt = IPU_PIX_FMT_LVDS666,
369 .detect = detect_i2c,
370 .enable = enable_lvds,
371 .mode = {
372 .name = "Hannstar-XGA",
373 .refresh = 60,
374 .xres = 1024,
375 .yres = 768,
376 .pixclock = 15385,
377 .left_margin = 220,
378 .right_margin = 40,
379 .upper_margin = 21,
380 .lower_margin = 7,
381 .hsync_len = 60,
382 .vsync_len = 10,
383 .sync = FB_SYNC_EXT,
384 .vmode = FB_VMODE_NONINTERLACED
385} }, {
386
387 .bus = 0,
388 .addr = 0,
389 .detect = NULL,
390 .enable = enable_lvds,
391 .pixfmt = IPU_PIX_FMT_LVDS666,
392 .mode = {
393 .name = "DLC700JMGT4",
394 .refresh = 60,
395 .xres = 1024,
396 .yres = 600,
397 .pixclock = 15385,
398 .left_margin = 220,
399 .right_margin = 40,
400 .upper_margin = 21,
401 .lower_margin = 7,
402 .hsync_len = 60,
403 .vsync_len = 10,
404 .sync = FB_SYNC_EXT,
405 .vmode = FB_VMODE_NONINTERLACED
406} }, {
407
408 .bus = 0,
409 .addr = 0,
410 .detect = NULL,
411 .enable = enable_lvds,
412 .pixfmt = IPU_PIX_FMT_LVDS666,
413 .mode = {
414 .name = "DLC800FIGT3",
415 .refresh = 60,
416 .xres = 1024,
417 .yres = 768,
418 .pixclock = 15385,
419 .left_margin = 220,
420 .right_margin = 40,
421 .upper_margin = 21,
422 .lower_margin = 7,
423 .hsync_len = 60,
424 .vsync_len = 10,
425 .sync = FB_SYNC_EXT,
426 .vmode = FB_VMODE_NONINTERLACED
427} } };
428size_t display_count = ARRAY_SIZE(displays);
429
430static void setup_display(void)
431{
432 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
433 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
434 int reg;
435
436 enable_ipu_clock();
437 imx_setup_hdmi();
438
439 reg = __raw_readl(&mxc_ccm->CCGR3);
440 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
441 writel(reg, &mxc_ccm->CCGR3);
442
443
444 reg = readl(&mxc_ccm->cs2cdr);
445 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
446 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
447 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
448 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
449 writel(reg, &mxc_ccm->cs2cdr);
450
451 reg = readl(&mxc_ccm->cscmr2);
452 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
453 writel(reg, &mxc_ccm->cscmr2);
454
455 reg = readl(&mxc_ccm->chsccdr);
456 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
457 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
458 writel(reg, &mxc_ccm->chsccdr);
459
460 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
461 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
462 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
463 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
464 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
465 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
466 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
467 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
468 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
469 writel(reg, &iomux->gpr[2]);
470
471 reg = readl(&iomux->gpr[3]);
472 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
473 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
474 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
475 writel(reg, &iomux->gpr[3]);
476
477
478 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
479 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
480}
481#endif
482
483
484int power_init_board(void)
485{
486 setup_pmic();
487 return 0;
488}
489
490#if defined(CONFIG_CMD_PCI)
491int imx6_pcie_toggle_reset(void)
492{
493 if (board_type < GW_UNKNOWN) {
494 uint pin = gpio_cfg[board_type].pcie_rst;
495 gpio_request(pin, "pci_rst#");
496 gpio_direction_output(pin, 0);
497 mdelay(50);
498 gpio_direction_output(pin, 1);
499 }
500 return 0;
501}
502
503
504
505
506
507
508#define MAX_PCI_DEVS 32
509struct pci_dev {
510 pci_dev_t devfn;
511 unsigned short vendor;
512 unsigned short device;
513 unsigned short class;
514 unsigned short busno;
515 struct pci_dev *ppar;
516};
517struct pci_dev pci_devs[MAX_PCI_DEVS];
518int pci_devno;
519int pci_bridgeno;
520
521void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
522 unsigned short vendor, unsigned short device,
523 unsigned short class)
524{
525 int i;
526 u32 dw;
527 struct pci_dev *pdev = &pci_devs[pci_devno++];
528
529 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
530 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
531
532
533 pdev->devfn = dev;
534 pdev->vendor = vendor;
535 pdev->device = device;
536 pdev->class = class;
537 pdev->ppar = NULL;
538 if (class == PCI_CLASS_BRIDGE_PCI)
539 pdev->busno = ++pci_bridgeno;
540 else
541 pdev->busno = 0;
542
543
544 if (PCI_BUS(dev) == 0)
545 pdev->devfn = 0;
546
547
548 for (i = 0; i < pci_devno; i++) {
549 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
550 pdev->ppar = &pci_devs[i];
551 break;
552 }
553 }
554
555
556 if (vendor == PCI_VENDOR_ID_PLX &&
557 (device & 0xfff0) == 0x8600 &&
558 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
559 debug("configuring PLX 860X downstream PERST#\n");
560 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
561 dw |= 0xaaa8;
562 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
563
564 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
565 dw |= 0xfe;
566 pci_hose_write_config_dword(hose, dev, 0x644, dw);
567
568 mdelay(100);
569 }
570}
571#endif
572
573#ifdef CONFIG_SERIAL_TAG
574
575
576
577
578
579
580void get_board_serial(struct tag_serialnr *serialnr)
581{
582 char *serial = env_get("serial#");
583
584 if (serial) {
585 serialnr->high = 0;
586 serialnr->low = simple_strtoul(serial, NULL, 10);
587 } else if (ventana_info.model[0]) {
588 serialnr->high = 0;
589 serialnr->low = ventana_info.serial;
590 } else {
591 serialnr->high = 0;
592 serialnr->low = 0;
593 }
594}
595#endif
596
597
598
599
600
601int board_early_init_f(void)
602{
603 setup_iomux_uart();
604
605#if defined(CONFIG_VIDEO_IPUV3)
606 setup_display();
607#endif
608 return 0;
609}
610
611int dram_init(void)
612{
613 gd->ram_size = imx_ddr_size();
614 return 0;
615}
616
617int board_init(void)
618{
619 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
620
621 clrsetbits_le32(&iomuxc_regs->gpr[1],
622 IOMUXC_GPR1_OTG_ID_MASK,
623 IOMUXC_GPR1_OTG_ID_GPIO1);
624
625
626 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
627
628#ifdef CONFIG_CMD_NAND
629 setup_gpmi_nand();
630#endif
631#ifdef CONFIG_MXC_SPI
632 setup_spi();
633#endif
634 setup_ventana_i2c();
635
636#ifdef CONFIG_SATA
637 setup_sata();
638#endif
639
640 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
641
642 setup_iomux_gpio(board_type, &ventana_info);
643
644 return 0;
645}
646
647#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
648
649
650
651
652
653int checkboard(void)
654{
655 struct ventana_board_info *info = &ventana_info;
656 unsigned char buf[4];
657 const char *p;
658 int quiet;
659
660 quiet = 0;
661 p = env_get("quiet");
662 if (p)
663 quiet = simple_strtol(p, NULL, 10);
664 else
665 env_set("quiet", "0");
666
667 puts("\nGateworks Corporation Copyright 2014\n");
668 if (info->model[0]) {
669 printf("Model: %s\n", info->model);
670 printf("MFGDate: %02x-%02x-%02x%02x\n",
671 info->mfgdate[0], info->mfgdate[1],
672 info->mfgdate[2], info->mfgdate[3]);
673 printf("Serial:%d\n", info->serial);
674 } else {
675 puts("Invalid EEPROM - board will not function fully\n");
676 }
677 if (quiet)
678 return 0;
679
680
681 gsc_info(0);
682
683
684 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
685 printf("RTC: %d\n",
686 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
687 }
688
689 return 0;
690}
691#endif
692
693#ifdef CONFIG_CMD_BMODE
694
695
696
697
698
699
700
701
702
703
704
705
706static const struct boot_mode board_boot_modes[] = {
707
708 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
709 { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) },
710 { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) },
711 { NULL, 0 },
712};
713#endif
714
715
716int misc_init_r(void)
717{
718 struct ventana_board_info *info = &ventana_info;
719 char buf[256];
720 int i;
721
722
723 if (ventana_info.model[0]) {
724 char str[16], fdt[36];
725 char *p;
726 const char *cputype = "";
727
728
729
730
731
732
733
734 if (is_cpu_type(MXC_CPU_MX6Q) ||
735 is_cpu_type(MXC_CPU_MX6D))
736 cputype = "imx6q";
737 else if (is_cpu_type(MXC_CPU_MX6DL) ||
738 is_cpu_type(MXC_CPU_MX6SOLO))
739 cputype = "imx6dl";
740 env_set("soctype", cputype);
741 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
742 env_set("flash_layout", "large");
743 else
744 env_set("flash_layout", "normal");
745 memset(str, 0, sizeof(str));
746 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
747 str[i] = tolower(info->model[i]);
748 env_set("model", str);
749 if (!env_get("fdt_file")) {
750 sprintf(fdt, "%s-%s.dtb", cputype, str);
751 env_set("fdt_file", fdt);
752 }
753 p = strchr(str, '-');
754 if (p) {
755 *p++ = 0;
756
757 env_set("model_base", str);
758 sprintf(fdt, "%s-%s.dtb", cputype, str);
759 env_set("fdt_file1", fdt);
760 if (board_type != GW551x &&
761 board_type != GW552x &&
762 board_type != GW553x &&
763 board_type != GW560x)
764 str[4] = 'x';
765 str[5] = 'x';
766 str[6] = 0;
767 sprintf(fdt, "%s-%s.dtb", cputype, str);
768 env_set("fdt_file2", fdt);
769 }
770
771
772 if (test_bit(EECONFIG_ETH0, info->config) &&
773 !env_get("ethaddr")) {
774 eth_env_set_enetaddr("ethaddr", info->mac0);
775 }
776 if (test_bit(EECONFIG_ETH1, info->config) &&
777 !env_get("eth1addr")) {
778 eth_env_set_enetaddr("eth1addr", info->mac1);
779 }
780
781
782 sprintf(str, "%6d", info->serial);
783 env_set("serial#", str);
784
785
786 sprintf(str, "%d", (int) (gd->ram_size >> 20));
787 env_set("mem_mb", str);
788 }
789
790
791 if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
792 buf[0] = 0;
793 if (gpio_cfg[board_type].rs232_en)
794 strcat(buf, "rs232;");
795 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
796 char buf1[32];
797 sprintf(buf1, "dio%d:mode=gpio;", i);
798 if (strlen(buf) + strlen(buf1) < sizeof(buf))
799 strcat(buf, buf1);
800 }
801 env_set("hwconfig", buf);
802 }
803
804
805 setup_board_gpio(board_type, info);
806
807#ifdef CONFIG_CMD_BMODE
808 add_board_boot_modes(board_boot_modes);
809#endif
810
811
812 gsc_boot_wd_disable();
813
814 return 0;
815}
816
817#ifdef CONFIG_OF_BOARD_SETUP
818
819static int ft_sethdmiinfmt(void *blob, char *mode)
820{
821 int off;
822
823 if (!mode)
824 return -EINVAL;
825
826 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
827 if (off < 0)
828 return off;
829
830 if (0 == strcasecmp(mode, "yuv422bt656")) {
831 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
832 0x00, 0x00, 0x00 };
833 mode = "422_ccir";
834 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
835 fdt_setprop_u32(blob, off, "vidout_trc", 1);
836 fdt_setprop_u32(blob, off, "vidout_blc", 1);
837 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
838 printf(" set HDMI input mode to %s\n", mode);
839 } else if (0 == strcasecmp(mode, "yuv422smp")) {
840 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
841 0x82, 0x81, 0x00 };
842 mode = "422_smp";
843 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
844 fdt_setprop_u32(blob, off, "vidout_trc", 0);
845 fdt_setprop_u32(blob, off, "vidout_blc", 0);
846 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
847 printf(" set HDMI input mode to %s\n", mode);
848 } else {
849 return -EINVAL;
850 }
851
852 return 0;
853}
854
855
856static inline void ft_enable_path(void *blob, const char *path)
857{
858 int i = fdt_path_offset(blob, path);
859 if (i >= 0) {
860 debug("enabling %s\n", path);
861 fdt_status_okay(blob, i);
862 }
863}
864
865
866static inline void ft_delprop_path(void *blob, const char *path,
867 const char *name)
868{
869 int i = fdt_path_offset(blob, path);
870 if (i) {
871 debug("removing %s/%s\n", path, name);
872 fdt_delprop(blob, i, name);
873 }
874}
875
876#if defined(CONFIG_CMD_PCI)
877#define PCI_ID(x) ( \
878 (PCI_BUS(x->devfn)<<16)| \
879 (PCI_DEV(x->devfn)<<11)| \
880 (PCI_FUNC(x->devfn)<<8) \
881 )
882#define PCIE_PATH "/soc/pcie@0x01000000"
883int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
884{
885 uint32_t reg[5];
886 char node[32];
887 int np;
888
889 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
890 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
891
892 np = fdt_subnode_offset(blob, par, node);
893 if (np >= 0)
894 return np;
895 np = fdt_add_subnode(blob, par, node);
896 if (np < 0) {
897 printf(" %s failed: no space\n", __func__);
898 return np;
899 }
900
901 memset(reg, 0, sizeof(reg));
902 reg[0] = cpu_to_fdt32(PCI_ID(dev));
903 fdt_setprop(blob, np, "reg", reg, sizeof(reg));
904
905 return np;
906}
907
908
909int fdt_add_pci_path(void *blob, struct pci_dev *dev)
910{
911 struct pci_dev *bridges[MAX_PCI_DEVS];
912 int k, np;
913
914
915 np = fdt_path_offset(blob, PCIE_PATH);
916 if (np < 0)
917 return np;
918
919 k = 0;
920 while (dev) {
921 bridges[k++] = dev;
922 dev = dev->ppar;
923 };
924
925
926 while (k--) {
927 np = fdt_add_pci_node(blob, np, bridges[k]);
928 if (np < 0)
929 break;
930 }
931
932 return np;
933}
934
935
936
937
938
939
940
941int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
942{
943 int len;
944 int host;
945 uint32_t imap_new[8*4*4];
946 const uint32_t *imap;
947 uint32_t irq[4];
948 uint32_t reg[4];
949 int i;
950
951
952 host = fdt_path_offset(blob, PCIE_PATH);
953 if (host < 0) {
954 printf(" %s failed: missing host\n", __func__);
955 return host;
956 }
957
958
959 imap = fdt_getprop(blob, host, "interrupt-map", &len);
960 if (!imap || len != 128) {
961 printf(" %s failed: invalid interrupt-map\n",
962 __func__);
963 return -FDT_ERR_NOTFOUND;
964 }
965
966
967 for (i = 0; i < 4; i++)
968 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
969
970
971
972
973
974
975 struct pci_dev *d;
976 int b;
977 b = 0;
978 d = dev->ppar;
979 while(d && d->ppar) {
980 b += PCI_DEV(d->devfn);
981 d = d->ppar;
982 }
983
984
985
986
987
988
989
990
991 for (i = 0; i < 4; i++) {
992
993 u32 addr = dev->busno << 16 | (12+i) << 11;
994
995
996 memcpy(&imap_new[i*32], imap, 128);
997
998 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
999 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
1000 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
1001 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
1002
1003 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
1004 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
1005 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
1006 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
1007
1008 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
1009 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
1010 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
1011 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
1012 }
1013 fdt_setprop(blob, np, "interrupt-map", imap_new,
1014 sizeof(imap_new));
1015 reg[0] = cpu_to_fdt32(0xfff00);
1016 reg[1] = 0;
1017 reg[2] = 0;
1018 reg[3] = cpu_to_fdt32(0x7);
1019 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1020 fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1021 fdt_setprop_string(blob, np, "device_type", "pci");
1022 fdt_setprop_cell(blob, np, "#address-cells", 3);
1023 fdt_setprop_cell(blob, np, "#size-cells", 2);
1024 printf(" Added custom interrupt-map for GW16082\n");
1025
1026 return 0;
1027}
1028
1029
1030int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1031{
1032 char *tmp, *end;
1033 char mac[16];
1034 unsigned char mac_addr[6];
1035 int j;
1036
1037 sprintf(mac, "eth1addr");
1038 tmp = env_get(mac);
1039 if (tmp) {
1040 for (j = 0; j < 6; j++) {
1041 mac_addr[j] = tmp ?
1042 simple_strtoul(tmp, &end,16) : 0;
1043 if (tmp)
1044 tmp = (*end) ? end+1 : end;
1045 }
1046 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1047 sizeof(mac_addr));
1048 printf(" Added mac addr for eth1\n");
1049 return 0;
1050 }
1051
1052 return -1;
1053}
1054
1055
1056
1057
1058
1059
1060void ft_board_pci_fixup(void *blob, bd_t *bd)
1061{
1062 int i, np;
1063 struct pci_dev *dev;
1064
1065 for (i = 0; i < pci_devno; i++) {
1066 dev = &pci_devs[i];
1067
1068
1069
1070
1071
1072 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1073 (dev->device == 0x8240) &&
1074 (i2c_set_bus_num(1) == 0) &&
1075 (i2c_probe(0x50) == 0))
1076 {
1077 np = fdt_add_pci_path(blob, dev);
1078 if (np > 0)
1079 fdt_fixup_gw16082(blob, np, dev);
1080 }
1081
1082
1083 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1084 (dev->device == 0x4380))
1085 {
1086 np = fdt_add_pci_path(blob, dev);
1087 if (np > 0)
1088 fdt_fixup_sky2(blob, np, dev);
1089 }
1090 }
1091}
1092#endif
1093
1094void ft_board_wdog_fixup(void *blob, const char *path)
1095{
1096 ft_delprop_path(blob, path, "ext-reset-output");
1097 ft_delprop_path(blob, path, "fsl,ext-reset-output");
1098}
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109#define UART1_PATH "/soc/aips-bus@02100000/serial@021ec000"
1110#define WDOG1_PATH "/soc/aips-bus@02000000/wdog@020bc000"
1111#define WDOG2_PATH "/soc/aips-bus@02000000/wdog@020c0000"
1112#define GPIO3_PATH "/soc/aips-bus@02000000/gpio@020a4000"
1113int ft_board_setup(void *blob, bd_t *bd)
1114{
1115 struct ventana_board_info *info = &ventana_info;
1116 struct ventana_eeprom_config *cfg;
1117 struct node_info nodes[] = {
1118 { "sst,w25q256", MTD_DEV_TYPE_NOR, },
1119 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1120 };
1121 const char *model = env_get("model");
1122 const char *display = env_get("display");
1123 int i;
1124 char rev = 0;
1125
1126
1127 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1128 if (ventana_info.model[i] >= 'A') {
1129 rev = ventana_info.model[i];
1130 break;
1131 }
1132 }
1133
1134 if (env_get("fdt_noauto")) {
1135 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1136 return 0;
1137 }
1138
1139 if (test_bit(EECONFIG_NAND, info->config)) {
1140
1141 puts(" Updating MTD partitions...\n");
1142 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1143 }
1144
1145
1146 if (display) {
1147 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1148 display) >= 0)
1149 printf(" Set display timings for %s...\n", display);
1150 }
1151
1152 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1153
1154
1155 fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1156 strlen(env_get("serial#")) + 1);
1157
1158
1159 fdt_setprop(blob, 0, "board", info->model,
1160 strlen((const char *)info->model) + 1);
1161
1162
1163 ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
1164
1165
1166
1167
1168 switch (board_type) {
1169 case GW51xx:
1170
1171
1172
1173
1174 if (rev >= 'A' && rev < 'C') {
1175 i = fdt_path_offset(blob, WDOG1_PATH);
1176 if (i)
1177 fdt_status_disabled(blob, i);
1178 }
1179
1180
1181 if (rev < 'E')
1182 ft_board_wdog_fixup(blob, WDOG1_PATH);
1183 break;
1184
1185 case GW52xx:
1186
1187 if (info->model[4] == '2') {
1188 u32 handle = 0;
1189 u32 *range = NULL;
1190
1191 i = fdt_node_offset_by_compatible(blob, -1,
1192 "fsl,imx6q-pcie");
1193 if (i)
1194 range = (u32 *)fdt_getprop(blob, i,
1195 "reset-gpio", NULL);
1196
1197 if (range) {
1198 i = fdt_path_offset(blob, GPIO3_PATH);
1199 if (i)
1200 handle = fdt_get_phandle(blob, i);
1201 if (handle) {
1202 range[0] = cpu_to_fdt32(handle);
1203 range[1] = cpu_to_fdt32(23);
1204 }
1205 }
1206
1207
1208 if (strstr((const char *)info->model, "SP318-B") ||
1209 strstr((const char *)info->model, "SP331-B"))
1210 gpio_cfg[board_type].usd_vsel = 0;
1211
1212
1213 ft_board_wdog_fixup(blob, WDOG1_PATH);
1214 }
1215
1216
1217 else if (info->model[4] == '0' && rev < 'E')
1218 ft_board_wdog_fixup(blob, WDOG1_PATH);
1219 break;
1220
1221 case GW53xx:
1222
1223 if (rev < 'E')
1224 ft_board_wdog_fixup(blob, WDOG1_PATH);
1225 break;
1226
1227 case GW54xx:
1228
1229
1230
1231
1232 i = fdt_path_offset(blob, UART1_PATH);
1233 if (i)
1234 fdt_del_node(blob, i);
1235
1236
1237 if (rev < 'E')
1238 ft_board_wdog_fixup(blob, WDOG2_PATH);
1239 break;
1240
1241 case GW551x:
1242
1243
1244
1245
1246 if (rev == 'A') {
1247 u32 *range = NULL;
1248 int len;
1249 const u32 *handle = NULL;
1250
1251 i = fdt_node_offset_by_compatible(blob, -1,
1252 "fsl,imx-tda1997x-video");
1253 if (i)
1254 handle = fdt_getprop(blob, i, "pinctrl-0",
1255 NULL);
1256 if (handle)
1257 i = fdt_node_offset_by_phandle(blob,
1258 fdt32_to_cpu(*handle));
1259 if (i)
1260 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1261 &len);
1262 if (range) {
1263 len /= sizeof(u32);
1264 for (i = 0; i < len; i += 6) {
1265 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1266 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1267
1268 if (is_cpu_type(MXC_CPU_MX6Q) &&
1269 mux_reg == 0x260 &&
1270 conf_reg == 0x630)
1271 range[i+3] = cpu_to_fdt32(0x5);
1272 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1273 mux_reg == 0x08c &&
1274 conf_reg == 0x3a0)
1275 range[i+3] = cpu_to_fdt32(0x5);
1276 }
1277 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1278 len);
1279 }
1280
1281
1282 ft_sethdmiinfmt(blob, "yuv422bt656");
1283 }
1284
1285
1286 if (rev < 'C')
1287 ft_board_wdog_fixup(blob, WDOG1_PATH);
1288 break;
1289 }
1290
1291
1292 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1293 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1294 char arg[10];
1295
1296 sprintf(arg, "dio%d", i);
1297 if (!hwconfig(arg))
1298 continue;
1299 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1300 {
1301 char path[48];
1302 sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
1303 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
1304 printf(" Enabling pwm%d for DIO%d\n",
1305 cfg->pwm_param, i);
1306 ft_enable_path(blob, path);
1307 }
1308 }
1309
1310
1311 if (gpio_cfg[board_type].usd_vsel) {
1312 debug("Enabling UHS-I support\n");
1313 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
1314 "no-1-8-v");
1315 }
1316
1317#if defined(CONFIG_CMD_PCI)
1318 if (!env_get("nopcifixup"))
1319 ft_board_pci_fixup(blob, bd);
1320#endif
1321
1322
1323
1324
1325
1326
1327 if (env_get("fdt_noconfig")) {
1328 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
1329 return 0;
1330 }
1331 cfg = econfig;
1332 while (cfg->name) {
1333 if (!test_bit(cfg->bit, info->config)) {
1334 fdt_del_node_and_alias(blob, cfg->dtalias ?
1335 cfg->dtalias : cfg->name);
1336 }
1337 cfg++;
1338 }
1339
1340 return 0;
1341}
1342#endif
1343
1344static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1345 .reg = (struct mxc_uart *)UART2_BASE,
1346};
1347
1348U_BOOT_DEVICE(ventana_serial) = {
1349 .name = "serial_mxc",
1350 .platdata = &ventana_mxc_serial_plat,
1351};
1352
