1/* 2 * sbc8349.c -- WindRiver SBC8349 board support. 3 * Copyright (c) 2006-2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.) 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11#include <common.h> 12#include <ioports.h> 13#include <mpc83xx.h> 14#include <asm/mpc8349_pci.h> 15#include <i2c.h> 16#include <spd_sdram.h> 17#include <miiphy.h> 18#if defined(CONFIG_OF_LIBFDT) 19#include <libfdt.h> 20#endif 21 22DECLARE_GLOBAL_DATA_PTR; 23 24int fixed_sdram(void); 25void sdram_init(void); 26 27#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx) 28void ddr_enable_ecc(unsigned int dram_size); 29#endif 30 31#ifdef CONFIG_BOARD_EARLY_INIT_F 32int board_early_init_f (void) 33{ 34 return 0; 35} 36#endif 37 38#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) 39 40int dram_init(void) 41{ 42 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 43 u32 msize = 0; 44 45 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 46 return -1; 47 48 /* DDR SDRAM - Main SODIMM */ 49 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 50#if defined(CONFIG_SPD_EEPROM) 51 msize = spd_sdram(); 52#else 53 msize = fixed_sdram(); 54#endif 55 /* 56 * Initialize SDRAM if it is on local bus. 57 */ 58 sdram_init(); 59 60#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 61 /* 62 * Initialize and enable DDR ECC. 63 */ 64 ddr_enable_ecc(msize * 1024 * 1024); 65#endif 66 /* set total bus SDRAM size(bytes) -- DDR */ 67 gd->ram_size = msize * 1024 * 1024; 68 69 return 0; 70} 71 72#if !defined(CONFIG_SPD_EEPROM) 73/************************************************************************* 74 * fixed sdram init -- doesn't use serial presence detect. 75 ************************************************************************/ 76int fixed_sdram(void) 77{ 78 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 79 u32 msize = CONFIG_SYS_DDR_SIZE; 80 u32 ddr_size = msize << 20; /* DDR size in bytes */ 81 u32 ddr_size_log2 = __ilog2(msize); 82 83 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 84 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 85 86#if (CONFIG_SYS_DDR_SIZE != 256) 87#warning Currently any ddr size other than 256 is not supported 88#endif 89 90#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) 91#warning Chip select bounds is only configurable in 16MB increments 92#endif 93 im->ddr.csbnds[2].csbnds = 94 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | 95 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> 96 CSBNDS_EA_SHIFT) & CSBNDS_EA); 97 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; 98 99 /* currently we use only one CS, so disable the other banks */ 100 im->ddr.cs_config[0] = 0; 101 im->ddr.cs_config[1] = 0; 102 im->ddr.cs_config[3] = 0; 103 104 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 105 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 106 107 im->ddr.sdram_cfg = 108 SDRAM_CFG_SREN 109#if defined(CONFIG_DDR_2T_TIMING) 110 | SDRAM_CFG_2T_EN 111#endif 112 | SDRAM_CFG_SDRAM_TYPE_DDR1; 113#if defined (CONFIG_DDR_32BIT) 114 /* for 32-bit mode burst length is 8 */ 115 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); 116#endif 117 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 118 119 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 120 udelay(200); 121 122 /* enable DDR controller */ 123 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 124 return msize; 125} 126#endif/*!CONFIG_SYS_SPD_EEPROM*/ 127 128 129int checkboard (void) 130{ 131 puts("Board: Wind River SBC834x\n"); 132 return 0; 133} 134 135/* 136 * if board is fitted with SDRAM 137 */ 138#if defined(CONFIG_SYS_BR2_PRELIM) \ 139 && defined(CONFIG_SYS_OR2_PRELIM) \ 140 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ 141 && defined(CONFIG_SYS_LBLAWAR2_PRELIM) 142/* 143 * Initialize SDRAM memory on the Local Bus. 144 */ 145 146void sdram_init(void) 147{ 148 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 149 volatile fsl_lbc_t *lbc = &immap->im_lbc; 150 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 151 152 puts("\n SDRAM on Local Bus: "); 153 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 154 155 /* 156 * Setup SDRAM Base and Option Registers, already done in cpu_init.c 157 */ 158 159 /* setup mtrpt, lsrt and lbcr for LB bus */ 160 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 161 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 162 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 163 asm("sync"); 164 165 /* 166 * Configure the SDRAM controller Machine Mode Register. 167 */ 168 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ 169 170 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ 171 asm("sync"); 172 *sdram_addr = 0xff; 173 udelay(100); 174 175 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ 176 asm("sync"); 177 /*1 times*/ 178 *sdram_addr = 0xff; 179 udelay(100); 180 /*2 times*/ 181 *sdram_addr = 0xff; 182 udelay(100); 183 /*3 times*/ 184 *sdram_addr = 0xff; 185 udelay(100); 186 /*4 times*/ 187 *sdram_addr = 0xff; 188 udelay(100); 189 /*5 times*/ 190 *sdram_addr = 0xff; 191 udelay(100); 192 /*6 times*/ 193 *sdram_addr = 0xff; 194 udelay(100); 195 /*7 times*/ 196 *sdram_addr = 0xff; 197 udelay(100); 198 /*8 times*/ 199 *sdram_addr = 0xff; 200 udelay(100); 201 202 /* 0x58636733; mode register write operation */ 203 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; 204 asm("sync"); 205 *sdram_addr = 0xff; 206 udelay(100); 207 208 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ 209 asm("sync"); 210 *sdram_addr = 0xff; 211 udelay(100); 212} 213#else 214void sdram_init(void) 215{ 216 puts(" SDRAM on Local Bus: Disabled in config\n"); 217} 218#endif 219 220#if defined(CONFIG_OF_BOARD_SETUP) 221int ft_board_setup(void *blob, bd_t *bd) 222{ 223 ft_cpu_setup(blob, bd); 224#ifdef CONFIG_PCI 225 ft_pci_setup(blob, bd); 226#endif 227 228 return 0; 229} 230#endif 231