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10#include <common.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/hardware.h>
13#include <asm/ti-common/keystone_net.h>
14
15DECLARE_GLOBAL_DATA_PTR;
16
17unsigned int external_clk[ext_clk_count] = {
18 [sys_clk] = 122880000,
19 [alt_core_clk] = 125000000,
20 [pa_clk] = 122880000,
21 [tetris_clk] = 125000000,
22 [ddr3a_clk] = 100000000,
23 [ddr3b_clk] = 100000000,
24};
25
26unsigned int get_external_clk(u32 clk)
27{
28 unsigned int clk_freq;
29
30 switch (clk) {
31 case sys_clk:
32 clk_freq = 122880000;
33 break;
34 case alt_core_clk:
35 clk_freq = 125000000;
36 break;
37 case pa_clk:
38 clk_freq = 122880000;
39 break;
40 case tetris_clk:
41 clk_freq = 125000000;
42 break;
43 case ddr3a_clk:
44 clk_freq = 100000000;
45 break;
46 case ddr3b_clk:
47 clk_freq = 100000000;
48 break;
49 default:
50 clk_freq = 0;
51 break;
52 }
53
54 return clk_freq;
55}
56
57static struct pll_init_data core_pll_config[NUM_SPDS] = {
58 [SPD800] = CORE_PLL_799,
59 [SPD1000] = CORE_PLL_999,
60 [SPD1200] = CORE_PLL_1200,
61};
62
63s16 divn_val[16] = {
64 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
65};
66
67static struct pll_init_data tetris_pll_config[] = {
68 [SPD800] = TETRIS_PLL_800,
69 [SPD1000] = TETRIS_PLL_1000,
70 [SPD1200] = TETRIS_PLL_1200,
71 [SPD1350] = TETRIS_PLL_1350,
72 [SPD1400] = TETRIS_PLL_1400,
73};
74
75static struct pll_init_data pa_pll_config =
76 PASS_PLL_983;
77
78struct pll_init_data *get_pll_init_data(int pll)
79{
80 int speed;
81 struct pll_init_data *data;
82
83 switch (pll) {
84 case MAIN_PLL:
85 speed = get_max_dev_speed(speeds);
86 data = &core_pll_config[speed];
87 break;
88 case TETRIS_PLL:
89 speed = get_max_arm_speed(speeds);
90 data = &tetris_pll_config[speed];
91 break;
92 case PASS_PLL:
93 data = &pa_pll_config;
94 break;
95 default:
96 data = NULL;
97 }
98
99 return data;
100}
101
102#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
103struct eth_priv_t eth_priv_cfg[] = {
104 {
105 .int_name = "K2HK_EMAC",
106 .rx_flow = 22,
107 .phy_addr = 0,
108 .slave_port = 1,
109 .sgmii_link_type = SGMII_LINK_MAC_PHY,
110 .phy_if = PHY_INTERFACE_MODE_SGMII,
111 },
112 {
113 .int_name = "K2HK_EMAC1",
114 .rx_flow = 23,
115 .phy_addr = 1,
116 .slave_port = 2,
117 .sgmii_link_type = SGMII_LINK_MAC_PHY,
118 .phy_if = PHY_INTERFACE_MODE_SGMII,
119 },
120 {
121 .int_name = "K2HK_EMAC2",
122 .rx_flow = 24,
123 .phy_addr = 2,
124 .slave_port = 3,
125 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
126 .phy_if = PHY_INTERFACE_MODE_SGMII,
127 },
128 {
129 .int_name = "K2HK_EMAC3",
130 .rx_flow = 25,
131 .phy_addr = 3,
132 .slave_port = 4,
133 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
134 .phy_if = PHY_INTERFACE_MODE_SGMII,
135 },
136};
137
138int get_num_eth_ports(void)
139{
140 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
141}
142#endif
143
144#ifdef CONFIG_BOARD_EARLY_INIT_F
145int board_early_init_f(void)
146{
147 init_plls();
148
149 return 0;
150}
151#endif
152
153#if defined(CONFIG_FIT_EMBED)
154int board_fit_config_name_match(const char *name)
155{
156 if (!strcmp(name, "keystone-k2hk-evm"))
157 return 0;
158
159 return -1;
160}
161#endif
162
163#ifdef CONFIG_SPL_BUILD
164void spl_init_keystone_plls(void)
165{
166 init_plls();
167}
168#endif
169
