LXR uboot/drivers/pinctrl/nxp/pinctrl-imx.c

   1/*
   2 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <mapmem.h>
   9#include <linux/io.h>
  10#include <linux/err.h>
  11#include <dm.h>
  12#include <dm/pinctrl.h>
  13
  14#include "pinctrl-imx.h"
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  19{
  20        struct imx_pinctrl_priv *priv = dev_get_priv(dev);
  21        struct imx_pinctrl_soc_info *info = priv->info;
  22        int node = dev_of_offset(config);
  23        const struct fdt_property *prop;
  24        u32 *pin_data;
  25        int npins, size, pin_size;
  26        int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val;
  27        u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
  28        int i, j = 0;
  29
  30        dev_dbg(dev, "%s: %s\n", __func__, config->name);
  31
  32        if (info->flags & SHARE_MUX_CONF_REG)
  33                pin_size = SHARE_FSL_PIN_SIZE;
  34        else
  35                pin_size = FSL_PIN_SIZE;
  36
  37        prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
  38        if (!prop) {
  39                dev_err(dev, "No fsl,pins property in node %s\n", config->name);
  40                return -EINVAL;
  41        }
  42
  43        if (!size || size % pin_size) {
  44                dev_err(dev, "Invalid fsl,pins property in node %s\n",
  45                        config->name);
  46                return -EINVAL;
  47        }
  48
  49        pin_data = devm_kzalloc(dev, size, 0);
  50        if (!pin_data)
  51                return -ENOMEM;
  52
  53        if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
  54                                 pin_data, size >> 2)) {
  55                dev_err(dev, "Error reading pin data.\n");
  56                devm_kfree(dev, pin_data);
  57                return -EINVAL;
  58        }
  59
  60        npins = size / pin_size;
  61
  62        /*
  63         * Refer to linux documentation for details:
  64         * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
  65         */
  66        for (i = 0; i < npins; i++) {
  67                mux_reg = pin_data[j++];
  68
  69                if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
  70                        mux_reg = -1;
  71
  72                if (info->flags & SHARE_MUX_CONF_REG) {
  73                        conf_reg = mux_reg;
  74                } else {
  75                        conf_reg = pin_data[j++];
  76                        if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
  77                                conf_reg = -1;
  78                }
  79
  80                if ((mux_reg == -1) || (conf_reg == -1)) {
  81                        dev_err(dev, "Error mux_reg or conf_reg\n");
  82                        devm_kfree(dev, pin_data);
  83                        return -EINVAL;
  84                }
  85
  86                input_reg = pin_data[j++];
  87                mux_mode = pin_data[j++];
  88                input_val = pin_data[j++];
  89                config_val = pin_data[j++];
  90
  91                dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, "
  92                        "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n",
  93                        mux_reg, conf_reg, input_reg, mux_mode, input_val,
  94                        config_val);
  95
  96                if (config_val & IMX_PAD_SION)
  97                        mux_mode |= IOMUXC_CONFIG_SION;
  98
  99                config_val &= ~IMX_PAD_SION;
 100
 101                /* Set Mux */
 102                if (info->flags & SHARE_MUX_CONF_REG) {
 103                        clrsetbits_le32(info->base + mux_reg, info->mux_mask,
 104                                        mux_mode << mux_shift);
 105                } else {
 106                        writel(mux_mode, info->base + mux_reg);
 107                }
 108
 109                dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg,
 110                        mux_mode);
 111
 112                /*
 113                 * Set select input
 114                 *
 115                 * If the select input value begins with 0xff, it's a quirky
 116                 * select input and the value should be interpreted as below.
 117                 *     31     23      15      7        0
 118                 *     | 0xff | shift | width | select |
 119                 * It's used to work around the problem that the select
 120                 * input for some pin is not implemented in the select
 121                 * input register but in some general purpose register.
 122                 * We encode the select input value, width and shift of
 123                 * the bit field into input_val cell of pin function ID
 124                 * in device tree, and then decode them here for setting
 125                 * up the select input bits in general purpose register.
 126                 */
 127
 128                if (input_val >> 24 == 0xff) {
 129                        u32 val = input_val;
 130                        u8 select = val & 0xff;
 131                        u8 width = (val >> 8) & 0xff;
 132                        u8 shift = (val >> 16) & 0xff;
 133                        u32 mask = ((1 << width) - 1) << shift;
 134                        /*
 135                         * The input_reg[i] here is actually some IOMUXC general
 136                         * purpose register, not regular select input register.
 137                         */
 138                        val = readl(info->base + input_reg);
 139                        val &= ~mask;
 140                        val |= select << shift;
 141                        writel(val, info->base + input_reg);
 142                } else if (input_reg) {
 143                        /*
 144                         * Regular select input register can never be at offset
 145                         * 0, and we only print register value for regular case.
 146                         */
 147                        if (info->input_sel_base)
 148                                writel(input_val, info->input_sel_base +
 149                                       input_reg);
 150                        else
 151                                writel(input_val, info->base + input_reg);
 152
 153                        dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n",
 154                                input_reg, input_val);
 155                }
 156
 157                /* Set config */
 158                if (!(config_val & IMX_NO_PAD_CTL)) {
 159                        if (info->flags & SHARE_MUX_CONF_REG) {
 160                                clrsetbits_le32(info->base + conf_reg,
 161                                                ~info->mux_mask, config_val);
 162                        } else {
 163                                writel(config_val, info->base + conf_reg);
 164                        }
 165
 166                        dev_dbg(dev, "write config: offset 0x%x val 0x%x\n",
 167                                conf_reg, config_val);
 168                }
 169        }
 170
 171        devm_kfree(dev, pin_data);
 172
 173        return 0;
 174}
 175
 176const struct pinctrl_ops imx_pinctrl_ops  = {
 177        .set_state = imx_pinctrl_set_state,
 178};
 179
 180int imx_pinctrl_probe(struct udevice *dev,
 181                      struct imx_pinctrl_soc_info *info)
 182{
 183        struct imx_pinctrl_priv *priv = dev_get_priv(dev);
 184        int node = dev_of_offset(dev), ret;
 185        struct fdtdec_phandle_args arg;
 186        fdt_addr_t addr;
 187        fdt_size_t size;
 188
 189        if (!info) {
 190                dev_err(dev, "wrong pinctrl info\n");
 191                return -EINVAL;
 192        }
 193
 194        priv->dev = dev;
 195        priv->info = info;
 196
 197        addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
 198                                    &size);
 199
 200        if (addr == FDT_ADDR_T_NONE)
 201                return -EINVAL;
 202
 203        info->base = map_sysmem(addr, size);
 204        if (!info->base)
 205                return -ENOMEM;
 206        priv->info = info;
 207
 208        info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
 209        /*
 210         * Refer to linux documentation for details:
 211         * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
 212         */
 213        if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
 214                ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
 215                                                     node, "fsl,input-sel",
 216                                                     NULL, 0, 0, &arg);
 217                if (ret) {
 218                        dev_err(dev, "iomuxc fsl,input-sel property not found\n");
 219                        return -EINVAL;
 220                }
 221
 222                addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
 223                                            &size);
 224                if (addr == FDT_ADDR_T_NONE)
 225                        return -EINVAL;
 226
 227                info->input_sel_base = map_sysmem(addr, size);
 228                if (!info->input_sel_base)
 229                        return -ENOMEM;
 230        }
 231
 232        dev_dbg(dev, "initialized IMX pinctrl driver\n");
 233
 234        return 0;
 235}
 236
 237int imx_pinctrl_remove(struct udevice *dev)
 238{
 239        struct imx_pinctrl_priv *priv = dev_get_priv(dev);
 240        struct imx_pinctrl_soc_info *info = priv->info;
 241
 242        if (info->input_sel_base)
 243                unmap_sysmem(info->input_sel_base);
 244        if (info->base)
 245                unmap_sysmem(info->base);
 246
 247        return 0;
 248}
 249