LXR uboot/include/configs/ti_omap5

   1/*
   2 * (C) Copyright 2013
   3 * Texas Instruments Incorporated.
   4 * Sricharan R    <r.sricharan@ti.com>
   5 *
   6 * Derived from OMAP4 done by:
   7 *      Aneesh V <aneesh@ti.com>
   8 *
   9 * TI OMAP5 AND DRA7XX common configuration settings
  10 *
  11 * SPDX-License-Identifier:     GPL-2.0+
  12 *
  13 * For more details, please see the technical documents listed at
  14 * http://www.ti.com/product/omap5432
  15 */
  16
  17#ifndef __CONFIG_TI_OMAP5_COMMON_H
  18#define __CONFIG_TI_OMAP5_COMMON_H
  19
  20/* Use General purpose timer 1 */
  21#define CONFIG_SYS_TIMERBASE            GPT2_BASE
  22
  23/*
  24 * For the DDR timing information we can either dynamically determine
  25 * the timings to use or use pre-determined timings (based on using the
  26 * dynamic method.  Default to the static timing infomation.
  27 */
  28#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  29#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  30#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
  31#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
  32#endif
  33
  34#define CONFIG_PALMAS_POWER
  35
  36#include <asm/arch/cpu.h>
  37#include <asm/arch/omap.h>
  38
  39#include <configs/ti_armv7_omap.h>
  40
  41/*
  42 * Hardware drivers
  43 */
  44#define CONFIG_SYS_NS16550_CLK          48000000
  45#if !defined(CONFIG_DM_SERIAL)
  46#define CONFIG_SYS_NS16550_SERIAL
  47#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  48#endif
  49
  50/*
  51 * Environment setup
  52 */
  53
  54#ifndef DFUARGS
  55#define DFUARGS
  56#endif
  57
  58#include <environment/ti/boot.h>
  59#include <environment/ti/mmc.h>
  60
  61#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  62#define CONFIG_EXTRA_ENV_SETTINGS \
  63        DEFAULT_LINUX_BOOT_ENV \
  64        DEFAULT_MMC_TI_ARGS \
  65        DEFAULT_FIT_TI_ARGS \
  66        DEFAULT_COMMON_BOOT_TI_ARGS \
  67        DEFAULT_FDT_TI_ARGS \
  68        DFUARGS \
  69        NETARGS \
  70
  71/*
  72 * SPL related defines.  The Public RAM memory map the ROM defines the
  73 * area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
  74 * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
  75 * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
  76 * print some information.
  77 */
  78#ifdef CONFIG_TI_SECURE_DEVICE
  79/*
  80 * For memory booting on HS parts, the first 4KB of the internal RAM is
  81 * reserved for secure world use and the flash loader image is
  82 * preceded by a secure certificate. The SPL will therefore run in internal
  83 * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
  84 */
  85#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ       0x1000
  86#define CONFIG_SPL_TEXT_BASE    0x40301350
  87/* If no specific start address is specified then the secure EMIF
  88 * region will be placed at the end of the DDR space. In order to prevent
  89 * the main u-boot relocation from clobbering that memory and causing a
  90 * firewall violation, we tell u-boot that memory is protected RAM (PRAM)
  91 */
  92#if (CONFIG_TI_SECURE_EMIF_REGION_START == 0)
  93#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10
  94#endif
  95#else
  96/*
  97 * For all booting on GP parts, the flash loader image is
  98 * downloaded into internal RAM at address 0x40300000.
  99 */
 100#define CONFIG_SPL_TEXT_BASE    0x40300000
 101#endif
 102
 103#define CONFIG_SYS_SPL_ARGS_ADDR        (CONFIG_SYS_SDRAM_BASE + \
 104                                         (128 << 20))
 105
 106#ifdef CONFIG_NAND
 107#define CONFIG_SPL_NAND_AM33XX_BCH      /* ELM support */
 108#endif
 109
 110#ifdef CONFIG_SPL_BUILD
 111#undef CONFIG_TIMER
 112#endif
 113
 114#endif /* __CONFIG_TI_OMAP5_COMMON_H */
 115