1
2
3
4
5
6
7
8#include <common.h>
9#include <mmc.h>
10#include <fsl_esdhc.h>
11#include <miiphy.h>
12#include <netdev.h>
13#include <asm/io.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/imx-regs.h>
16#include <asm/arch/iomux.h>
17#include <asm/arch/mx6-pins.h>
18#include <asm/arch/crm_regs.h>
19#include <asm/arch/sys_proto.h>
20#include <asm/gpio.h>
21#include <asm/mach-imx/iomux-v3.h>
22#include <asm/mach-imx/boot_mode.h>
23
24#include "platinum.h"
25
26DECLARE_GLOBAL_DATA_PTR;
27
28iomux_v3_cfg_t const usdhc3_pads[] = {
29 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
30 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
31 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
32 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
33 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
34 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
35 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
36};
37
38iomux_v3_cfg_t nfc_pads[] = {
39 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
40 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
41 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
42 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
43 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
44 MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
45 MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
46 MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
47 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
48 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
49 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
50 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
51 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
52 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
53 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
54 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
55 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
56 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
57 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
58};
59
60struct fsl_esdhc_cfg usdhc_cfg[] = {
61 { USDHC3_BASE_ADDR },
62};
63
64void setup_gpmi_nand(void)
65{
66 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
67
68
69 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
70
71
72 clrsetbits_le32(&mxc_ccm->cs2cdr,
73 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
74 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
75 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
76 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
77 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
78 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
79
80
81 setbits_le32(&mxc_ccm->CCGR4,
82 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
83 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
84 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
85 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
86 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
87
88
89 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
90}
91
92int dram_init(void)
93{
94 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
95
96 return 0;
97}
98
99int board_ehci_hcd_init(int port)
100{
101 return 0;
102}
103
104int board_mmc_getcd(struct mmc *mmc)
105{
106 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
107
108 if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) {
109 unsigned sd3_cd = IMX_GPIO_NR(7, 0);
110 gpio_direction_input(sd3_cd);
111 return !gpio_get_value(sd3_cd);
112 }
113
114 return 0;
115}
116
117int board_mmc_init(bd_t *bis)
118{
119 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
120 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
121
122 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
123}
124
125void board_init_gpio(void)
126{
127 platinum_init_gpio();
128}
129
130void board_init_gpmi_nand(void)
131{
132 setup_gpmi_nand();
133}
134
135void board_init_i2c(void)
136{
137 platinum_setup_i2c();
138}
139
140void board_init_spi(void)
141{
142 platinum_setup_spi();
143}
144
145void board_init_uart(void)
146{
147 platinum_setup_uart();
148}
149
150void board_init_usb(void)
151{
152 platinum_init_usb();
153}
154
155void board_init_finished(void)
156{
157 platinum_init_finished();
158}
159
160int board_phy_config(struct phy_device *phydev)
161{
162 return platinum_phy_config(phydev);
163}
164
165int board_eth_init(bd_t *bis)
166{
167 return cpu_eth_init(bis);
168}
169
170int board_early_init_f(void)
171{
172 board_init_uart();
173
174 return 0;
175}
176
177int board_init(void)
178{
179
180 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
181
182 board_init_spi();
183
184 board_init_i2c();
185
186 board_init_gpmi_nand();
187
188 board_init_gpio();
189
190 board_init_usb();
191
192 board_init_finished();
193
194 return 0;
195}
196
197int checkboard(void)
198{
199 puts("Board: " CONFIG_PLATINUM_BOARD "\n");
200 return 0;
201}
202
203static const struct boot_mode board_boot_modes[] = {
204
205 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
206
207 { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
208 { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
209 { NULL, 0 },
210};
211
212int misc_init_r(void)
213{
214 add_board_boot_modes(board_boot_modes);
215
216 return 0;
217}
218
