LXR uboot/board/freescale/t1040qds/ddr.c

   1/*
   2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <i2c.h>
   9#include <hwconfig.h>
  10#include <asm/mmu.h>
  11#include <fsl_ddr_sdram.h>
  12#include <fsl_ddr_dimm_params.h>
  13#include <asm/fsl_law.h>
  14#include <asm/mpc85xx_gpio.h>
  15#include "ddr.h"
  16
  17DECLARE_GLOBAL_DATA_PTR;
  18
  19void fsl_ddr_board_options(memctl_options_t *popts,
  20                                dimm_params_t *pdimm,
  21                                unsigned int ctrl_num)
  22{
  23        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  24        ulong ddr_freq;
  25
  26        if (ctrl_num > 2) {
  27                printf("Not supported controller number %d\n", ctrl_num);
  28                return;
  29        }
  30        if (!pdimm->n_ranks)
  31                return;
  32
  33        pbsp = udimms[0];
  34
  35        /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
  36         * freqency and n_banks specified in board_specific_parameters table.
  37         */
  38        ddr_freq = get_ddr_freq(0) / 1000000;
  39        while (pbsp->datarate_mhz_high) {
  40                if (pbsp->n_ranks == pdimm->n_ranks &&
  41                    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  42                        if (ddr_freq <= pbsp->datarate_mhz_high) {
  43                                popts->clk_adjust = pbsp->clk_adjust;
  44                                popts->wrlvl_start = pbsp->wrlvl_start;
  45                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  46                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  47                                goto found;
  48                        }
  49                        pbsp_highest = pbsp;
  50                }
  51                pbsp++;
  52        }
  53
  54        if (pbsp_highest) {
  55                printf("Error: board specific timing not found\n");
  56                printf("for data rate %lu MT/s\n", ddr_freq);
  57                printf("Trying to use the highest speed (%u) parameters\n",
  58                       pbsp_highest->datarate_mhz_high);
  59                popts->clk_adjust = pbsp_highest->clk_adjust;
  60                popts->wrlvl_start = pbsp_highest->wrlvl_start;
  61                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  62                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  63        } else {
  64                panic("DIMM is not supported by this board");
  65        }
  66found:
  67        debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  68                "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  69                "wrlvl_ctrl_3 0x%x\n",
  70                pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  71                pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  72                pbsp->wrlvl_ctl_3);
  73
  74        /*
  75         * Factors to consider for half-strength driver enable:
  76         *      - number of DIMMs installed
  77         */
  78        popts->half_strength_driver_enable = 1;
  79        /*
  80         * Write leveling override
  81         */
  82        popts->wrlvl_override = 1;
  83        popts->wrlvl_sample = 0xf;
  84
  85        /*
  86         * rtt and rtt_wr override
  87         */
  88        popts->rtt_override = 0;
  89
  90        /* Enable ZQ calibration */
  91        popts->zq_en = 1;
  92
  93        /* DHC_EN =1, ODT = 75 Ohm */
  94#ifdef CONFIG_SYS_FSL_DDR4
  95        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  96        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  97                          DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
  98
  99        /* optimize cpo for erratum A-009942 */
 100        popts->cpo_sample = 0x69;
 101#else
 102        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 103        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 104#endif
 105}
 106
 107#if defined(CONFIG_DEEP_SLEEP)
 108void board_mem_sleep_setup(void)
 109{
 110        void __iomem *qixis_base = (void *)QIXIS_BASE;
 111
 112        /* does not provide HW signals for power management */
 113        clrbits_8(qixis_base + 0x21, 0x2);
 114        /* Disable MCKE isolation */
 115        gpio_set_value(2, 0);
 116        udelay(1);
 117}
 118#endif
 119
 120int dram_init(void)
 121{
 122        phys_size_t dram_size;
 123
 124        puts("Initializing....using SPD\n");
 125
 126        dram_size = fsl_ddr_sdram();
 127
 128        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 129        dram_size *= 0x100000;
 130
 131        puts("    DDR: ");
 132
 133#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 134        fsl_dp_resume();
 135#endif
 136
 137        gd->ram_size = dram_size;
 138
 139        return 0;
 140}
 141