LXR uboot/board/freescale/t1040qds/ddr.h

   1/*
   2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#ifndef __DDR_H__
   8#define __DDR_H__
   9struct board_specific_parameters {
  10        u32 n_ranks;
  11        u32 datarate_mhz_high;
  12        u32 rank_gb;
  13        u32 clk_adjust;
  14        u32 wrlvl_start;
  15        u32 wrlvl_ctl_2;
  16        u32 wrlvl_ctl_3;
  17};
  18
  19/*
  20 * These tables contain all valid speeds we want to override with board
  21 * specific parameters. datarate_mhz_high values need to be in ascending order
  22 * for each n_ranks group.
  23 */
  24
  25static const struct board_specific_parameters udimm0[] = {
  26        /*
  27         * memory controller 0
  28         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
  29         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
  30         */
  31#ifdef CONFIG_SYS_FSL_DDR4
  32        {2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
  33        {2,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
  34        {1,  1666, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
  35        {1,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
  36        {1,  2200, 0, 8,     7, 0x08090A0D, 0x0F0F100C,},
  37#elif defined(CONFIG_SYS_FSL_DDR3)
  38        {2,  833,  0, 8,     6, 0x06060607, 0x08080807,},
  39        {2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
  40        {2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
  41        {1,  833,  0, 8,     6, 0x06060607, 0x08080807,},
  42        {1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
  43        {1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
  44#else
  45#error DDR type not defined
  46#endif
  47        {}
  48};
  49
  50static const struct board_specific_parameters *udimms[] = {
  51        udimm0,
  52};
  53#endif
  54