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6
7#include <common.h>
8#include <ahci.h>
9#include <netdev.h>
10#include <scsi.h>
11
12#include <linux/sizes.h>
13#include <asm/io.h>
14
15#define HB_AHCI_BASE 0xffe08000
16
17#define HB_SCU_A9_PWR_STATUS 0xfff10008
18#define HB_SREG_A9_PWR_REQ 0xfff3cf00
19#define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04
20#define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20
21#define HB_SREG_A15_PWR_CTRL 0xfff3c200
22
23#define HB_PWR_SUSPEND 0
24#define HB_PWR_SOFT_RESET 1
25#define HB_PWR_HARD_RESET 2
26#define HB_PWR_SHUTDOWN 3
27
28#define PWRDOM_STAT_SATA 0x80000000
29#define PWRDOM_STAT_PCI 0x40000000
30#define PWRDOM_STAT_EMMC 0x20000000
31
32#define HB_SCU_A9_PWR_NORMAL 0
33#define HB_SCU_A9_PWR_DORMANT 2
34#define HB_SCU_A9_PWR_OFF 3
35
36DECLARE_GLOBAL_DATA_PTR;
37
38void cphy_disable_overrides(void);
39
40
41
42
43int board_init(void)
44{
45 icache_enable();
46
47 return 0;
48}
49
50
51int board_eth_init(bd_t *bis)
52{
53 int rc = 0;
54
55#ifdef CONFIG_CALXEDA_XGMAC
56 rc += calxedaxgmac_initialize(0, 0xfff50000);
57 rc += calxedaxgmac_initialize(1, 0xfff51000);
58#endif
59 return rc;
60}
61
62#ifdef CONFIG_SCSI_AHCI_PLAT
63void scsi_init(void)
64{
65 u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
66
67 cphy_disable_overrides();
68 if (reg & PWRDOM_STAT_SATA) {
69 ahci_init((void __iomem *)HB_AHCI_BASE);
70 scsi_scan(true);
71 }
72}
73#endif
74
75#ifdef CONFIG_MISC_INIT_R
76int misc_init_r(void)
77{
78 char envbuffer[16];
79 u32 boot_choice;
80
81 boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
82 sprintf(envbuffer, "bootcmd%d", boot_choice);
83 if (env_get(envbuffer)) {
84 sprintf(envbuffer, "run bootcmd%d", boot_choice);
85 env_set("bootcmd", envbuffer);
86 } else
87 env_set("bootcmd", "");
88
89 return 0;
90}
91#endif
92
93int dram_init(void)
94{
95 gd->ram_size = SZ_512M;
96 return 0;
97}
98
99#if defined(CONFIG_OF_BOARD_SETUP)
100int ft_board_setup(void *fdt, bd_t *bd)
101{
102 static const char disabled[] = "disabled";
103 u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
104
105 if (!(reg & PWRDOM_STAT_SATA))
106 do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status",
107 disabled, sizeof(disabled), 1);
108
109 if (!(reg & PWRDOM_STAT_EMMC))
110 do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status",
111 disabled, sizeof(disabled), 1);
112
113 return 0;
114}
115#endif
116
117static int is_highbank(void)
118{
119 uint32_t midr;
120
121 asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
122
123 return (midr & 0xfff0) == 0xc090;
124}
125
126void reset_cpu(ulong addr)
127{
128 writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
129 if (is_highbank())
130 writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
131 else
132 writel(0x1, HB_SREG_A15_PWR_CTRL);
133
134 wfi();
135}
136
137
138
139
140
141void arch_preboot_os(void)
142{
143 cphy_disable_overrides();
144}
145