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17#include <common.h>
18#include <ioports.h>
19#include <mpc83xx.h>
20#include <i2c.h>
21#include <miiphy.h>
22#include <asm/io.h>
23#include <asm/mmu.h>
24#include <asm/processor.h>
25#include <pci.h>
26#include <libfdt.h>
27#include <post.h>
28
29#include "../common/common.h"
30
31DECLARE_GLOBAL_DATA_PTR;
32
33static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
34
35const qe_iop_conf_t qe_iop_conf_tab[] = {
36
37#if defined(CONFIG_MPC8360)
38
39 {0, 1, 3, 0, 2},
40 {0, 2, 1, 0, 1},
41
42
43 {1, 14, 1, 0, 1},
44 {1, 15, 1, 0, 1},
45 {1, 20, 2, 0, 1},
46 {1, 21, 2, 0, 1},
47 {1, 18, 1, 0, 1},
48 {1, 26, 2, 0, 1},
49 {1, 27, 2, 0, 1},
50 {1, 24, 2, 0, 1},
51 {1, 25, 2, 0, 1},
52 {2, 15, 2, 0, 1},
53 {2, 16, 2, 0, 1},
54
55
56 {5, 0, 1, 0, 2},
57 {5, 2, 1, 0, 1},
58 {5, 3, 2, 0, 2},
59 {5, 1, 2, 0, 3},
60#elif !defined(CONFIG_MPC8309)
61
62 {0, 16, 1, 0, 3},
63 {0, 17, 1, 0, 3},
64 {0, 18, 1, 0, 3},
65 {0, 19, 1, 0, 3},
66 {0, 20, 1, 0, 3},
67 {0, 21, 1, 0, 3},
68 {0, 22, 1, 0, 3},
69 {0, 23, 1, 0, 3},
70 {0, 24, 1, 0, 3},
71 {0, 25, 1, 0, 3},
72 {0, 26, 1, 0, 3},
73 {0, 27, 1, 0, 3},
74 {0, 28, 1, 0, 3},
75 {0, 29, 1, 0, 3},
76 {0, 30, 1, 0, 3},
77 {0, 31, 1, 0, 3},
78
79
80 {3, 4, 3, 0, 2},
81 {3, 5, 1, 0, 2},
82
83
84 {1, 18, 1, 0, 1},
85 {1, 19, 1, 0, 1},
86 {1, 22, 2, 0, 1},
87 {1, 23, 2, 0, 1},
88 {1, 26, 2, 0, 1},
89 {1, 28, 2, 0, 1},
90 {1, 30, 1, 0, 1},
91 {1, 31, 2, 0, 1},
92 {3, 10, 2, 0, 3},
93#endif
94
95
96 {0, 0, 0, 0, QE_IOP_TAB_END},
97};
98
99#if defined(CONFIG_SUVD3)
100const uint upma_table[] = {
101 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04,
102 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01,
103 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01,
104 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01,
105 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01,
106 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01,
107 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00,
108 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01,
109 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01,
110 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01,
111 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01,
112 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01,
113 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01,
114 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01,
115 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01,
116 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01
117};
118#endif
119
120static int piggy_present(void)
121{
122 struct km_bec_fpga __iomem *base =
123 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
124
125 return in_8(&base->bprth) & PIGGY_PRESENT;
126}
127
128#if defined(CONFIG_KMVECT1)
129int ethernet_present(void)
130{
131
132 return 1;
133}
134#else
135int ethernet_present(void)
136{
137 return piggy_present();
138}
139#endif
140
141
142int board_early_init_r(void)
143{
144 struct km_bec_fpga *base =
145 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
146#if defined(CONFIG_SUVD3)
147 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
148 fsl_lbc_t *lbc = &immap->im_lbc;
149 u32 *mxmr = &lbc->mamr;
150#endif
151
152#if defined(CONFIG_MPC8360)
153 unsigned short svid;
154
155
156
157
158 svid = SVR_REV(mfspr(SVR));
159 switch (svid) {
160 case 0x0020:
161
162
163
164
165
166 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
167 break;
168 case 0x0021:
169
170
171
172
173 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
174 0x00000050, 0x000000a0);
175 break;
176 }
177#endif
178
179
180 setbits_8(&base->pgy_eth, 0x01);
181
182 setbits_8(&base->oprth, WRL_BOOT);
183
184 setbits_8(&base->oprtl, OPRTL_XBUFENA);
185
186#if defined(CONFIG_SUVD3)
187
188 upmconfig(UPMA, (uint *) upma_table,
189 sizeof(upma_table) / sizeof(uint));
190 out_be32(mxmr, CONFIG_SYS_MAMR);
191#endif
192 return 0;
193}
194
195int misc_init_r(void)
196{
197 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
198 return 0;
199}
200
201#if defined(CONFIG_KMVECT1)
202#include <mv88e6352.h>
203
204static struct mv88e_sw_reg extsw_conf[] = {
205
206 { PORT(1), PORT_PHY, NO_SPEED_FOR },
207 { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
208 { PHY(1), PHY_1000_CTRL, NO_ADV },
209 { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN },
210 { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
211 FULL_DUPLEX },
212
213 { PORT(2), PORT_CTRL, PORT_DIS },
214 { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
215 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
216
217 { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
218
219 { PORT(4), PORT_STATUS, NO_PHY_DETECT },
220 { PORT(4), PORT_PHY, SPEED_1000_FOR },
221 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
222
223 { PORT(5), PORT_STATUS, NO_PHY_DETECT },
224 { PORT(5), PORT_PHY, SPEED_1000_FOR },
225 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
226
227
228
229
230 { PORT(5), 0x1A, 0xADB1 },
231
232 { PORT(6), PORT_CTRL, PORT_DIS },
233
234
235
236
237 { PORT(5), 0x1A, 0xADB1 },
238};
239#endif
240
241int last_stage_init(void)
242{
243#if defined(CONFIG_KMVECT1)
244 struct km_bec_fpga __iomem *base =
245 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
246 u8 tmp_reg;
247
248
249 tmp_reg = in_8(&base->res1[0]) | 0x10;
250 out_8(&base->res1[0], tmp_reg);
251 tmp_reg = in_8(&base->gprt3) | 0x10;
252 out_8(&base->gprt3, tmp_reg);
253
254
255 char *name = "UEC2";
256
257 if (miiphy_set_current_dev(name))
258 return 0;
259
260 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
261 ARRAY_SIZE(extsw_conf));
262
263 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
264
265 if (piggy_present()) {
266 env_set("ethact", "UEC2");
267 env_set("netdev", "eth1");
268 puts("using PIGGY for network boot\n");
269 } else {
270 env_set("netdev", "eth0");
271 puts("using frontport for network boot\n");
272 }
273#endif
274
275#if defined(CONFIG_KMCOGE5NE)
276 struct bfticu_iomap *base =
277 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
278 u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
279
280 if (dip_switch != 0) {
281
282 puts("DIP: Enabled\n");
283 env_set("actual_bank", "0");
284 }
285#endif
286 set_km_env();
287 return 0;
288}
289
290static int fixed_sdram(void)
291{
292 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
293 u32 msize = 0;
294 u32 ddr_size;
295 u32 ddr_size_log2;
296
297 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
298 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
299 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
300 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
301 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
302 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
303 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
304 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
305 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
306 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
307 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
308 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
309 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
310 udelay(200);
311 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
312
313 msize = CONFIG_SYS_DDR_SIZE << 20;
314 disable_addr_trans();
315 msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
316 enable_addr_trans();
317 msize /= (1024 * 1024);
318 if (CONFIG_SYS_DDR_SIZE != msize) {
319 for (ddr_size = msize << 20, ddr_size_log2 = 0;
320 (ddr_size > 1);
321 ddr_size = ddr_size >> 1, ddr_size_log2++)
322 if (ddr_size & 1)
323 return -1;
324 out_be32(&im->sysconf.ddrlaw[0].ar,
325 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
326 out_be32(&im->ddr.csbnds[0].csbnds,
327 (((msize / 16) - 1) & 0xff));
328 }
329
330 return msize;
331}
332
333int dram_init(void)
334{
335 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
336 u32 msize = 0;
337
338 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
339 return -ENXIO;
340
341 out_be32(&im->sysconf.ddrlaw[0].bar,
342 CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
343 msize = fixed_sdram();
344
345#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
346
347
348
349 ddr_enable_ecc(msize * 1024 * 1024);
350#endif
351
352
353 gd->ram_size = msize * 1024 * 1024;
354
355 return 0;
356}
357
358int checkboard(void)
359{
360 puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
361
362 if (piggy_present())
363 puts(" with PIGGY.");
364 puts("\n");
365 return 0;
366}
367
368int ft_board_setup(void *blob, bd_t *bd)
369{
370 ft_cpu_setup(blob, bd);
371
372 return 0;
373}
374
375#if defined(CONFIG_HUSH_INIT_VAR)
376int hush_init_var(void)
377{
378 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
379 return 0;
380}
381#endif
382
383#if defined(CONFIG_POST)
384int post_hotkeys_pressed(void)
385{
386 int testpin = 0;
387 struct km_bec_fpga *base =
388 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
389 int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
390 testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
391 debug("post_hotkeys_pressed: %d\n", !testpin);
392 return testpin;
393}
394
395ulong post_word_load(void)
396{
397 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
398 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
399 return in_le32(addr);
400
401}
402void post_word_store(ulong value)
403{
404 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
405 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
406 out_le32(addr, value);
407}
408
409int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
410{
411 *vstart = CONFIG_SYS_MEMTEST_START;
412 *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
413 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
414
415 return 0;
416}
417#endif
418