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12#include <config.h>
13#include <common.h>
14#include <command.h>
15#include <errno.h>
16#include <hwconfig.h>
17#include <mmc.h>
18#include <part.h>
19#include <power/regulator.h>
20#include <malloc.h>
21#include <fsl_esdhc.h>
22#include <fdt_support.h>
23#include <asm/io.h>
24#include <dm.h>
25#include <asm-generic/gpio.h>
26
27DECLARE_GLOBAL_DATA_PTR;
28
29#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
30 IRQSTATEN_CINT | \
31 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
32 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
33 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
34 IRQSTATEN_DINT)
35
36struct fsl_esdhc {
37 uint dsaddr;
38 uint blkattr;
39 uint cmdarg;
40 uint xfertyp;
41 uint cmdrsp0;
42 uint cmdrsp1;
43 uint cmdrsp2;
44 uint cmdrsp3;
45 uint datport;
46 uint prsstat;
47 uint proctl;
48 uint sysctl;
49 uint irqstat;
50 uint irqstaten;
51 uint irqsigen;
52 uint autoc12err;
53 uint hostcapblt;
54 uint wml;
55 uint mixctrl;
56 char reserved1[4];
57 uint fevt;
58 uint admaes;
59 uint adsaddr;
60 char reserved2[4];
61 uint dllctrl;
62 uint dllstat;
63 uint clktunectrlstatus;
64 char reserved3[84];
65 uint vendorspec;
66 uint mmcboot;
67 uint vendorspec2;
68 char reserved4[48];
69 uint hostver;
70 char reserved5[4];
71 uint dmaerraddr;
72 char reserved6[4];
73 uint dmaerrattr;
74 char reserved7[4];
75 uint hostcapblt2;
76 char reserved8[8];
77 uint tcr;
78 char reserved9[28];
79 uint sddirctl;
80 char reserved10[712];
81 uint scr;
82};
83
84struct fsl_esdhc_plat {
85 struct mmc_config cfg;
86 struct mmc mmc;
87};
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104
105struct fsl_esdhc_priv {
106 struct fsl_esdhc *esdhc_regs;
107 unsigned int sdhc_clk;
108 unsigned int bus_width;
109#if !CONFIG_IS_ENABLED(BLK)
110 struct mmc *mmc;
111#endif
112 struct udevice *dev;
113 int non_removable;
114 int wp_enable;
115 int vs18_enable;
116#ifdef CONFIG_DM_GPIO
117 struct gpio_desc cd_gpio;
118 struct gpio_desc wp_gpio;
119#endif
120};
121
122
123static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
124{
125 uint xfertyp = 0;
126
127 if (data) {
128 xfertyp |= XFERTYP_DPSEL;
129#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
130 xfertyp |= XFERTYP_DMAEN;
131#endif
132 if (data->blocks > 1) {
133 xfertyp |= XFERTYP_MSBSEL;
134 xfertyp |= XFERTYP_BCEN;
135#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
136 xfertyp |= XFERTYP_AC12EN;
137#endif
138 }
139
140 if (data->flags & MMC_DATA_READ)
141 xfertyp |= XFERTYP_DTDSEL;
142 }
143
144 if (cmd->resp_type & MMC_RSP_CRC)
145 xfertyp |= XFERTYP_CCCEN;
146 if (cmd->resp_type & MMC_RSP_OPCODE)
147 xfertyp |= XFERTYP_CICEN;
148 if (cmd->resp_type & MMC_RSP_136)
149 xfertyp |= XFERTYP_RSPTYP_136;
150 else if (cmd->resp_type & MMC_RSP_BUSY)
151 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
152 else if (cmd->resp_type & MMC_RSP_PRESENT)
153 xfertyp |= XFERTYP_RSPTYP_48;
154
155 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
156 xfertyp |= XFERTYP_CMDTYP_ABORT;
157
158 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
159}
160
161#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
162
163
164
165static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
166 struct mmc_data *data)
167{
168 struct fsl_esdhc *regs = priv->esdhc_regs;
169 uint blocks;
170 char *buffer;
171 uint databuf;
172 uint size;
173 uint irqstat;
174 ulong start;
175
176 if (data->flags & MMC_DATA_READ) {
177 blocks = data->blocks;
178 buffer = data->dest;
179 while (blocks) {
180 start = get_timer(0);
181 size = data->blocksize;
182 irqstat = esdhc_read32(®s->irqstat);
183 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
184 if (get_timer(start) > PIO_TIMEOUT) {
185 printf("\nData Read Failed in PIO Mode.");
186 return;
187 }
188 }
189 while (size && (!(irqstat & IRQSTAT_TC))) {
190 udelay(100);
191 irqstat = esdhc_read32(®s->irqstat);
192 databuf = in_le32(®s->datport);
193 *((uint *)buffer) = databuf;
194 buffer += 4;
195 size -= 4;
196 }
197 blocks--;
198 }
199 } else {
200 blocks = data->blocks;
201 buffer = (char *)data->src;
202 while (blocks) {
203 start = get_timer(0);
204 size = data->blocksize;
205 irqstat = esdhc_read32(®s->irqstat);
206 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
207 if (get_timer(start) > PIO_TIMEOUT) {
208 printf("\nData Write Failed in PIO Mode.");
209 return;
210 }
211 }
212 while (size && (!(irqstat & IRQSTAT_TC))) {
213 udelay(100);
214 databuf = *((uint *)buffer);
215 buffer += 4;
216 size -= 4;
217 irqstat = esdhc_read32(®s->irqstat);
218 out_le32(®s->datport, databuf);
219 }
220 blocks--;
221 }
222 }
223}
224#endif
225
226static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
227 struct mmc_data *data)
228{
229 int timeout;
230 struct fsl_esdhc *regs = priv->esdhc_regs;
231#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
232 dma_addr_t addr;
233#endif
234 uint wml_value;
235
236 wml_value = data->blocksize/4;
237
238 if (data->flags & MMC_DATA_READ) {
239 if (wml_value > WML_RD_WML_MAX)
240 wml_value = WML_RD_WML_MAX_VAL;
241
242 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
243#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
244#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
245 addr = virt_to_phys((void *)(data->dest));
246 if (upper_32_bits(addr))
247 printf("Error found for upper 32 bits\n");
248 else
249 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
250#else
251 esdhc_write32(®s->dsaddr, (u32)data->dest);
252#endif
253#endif
254 } else {
255#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
256 flush_dcache_range((ulong)data->src,
257 (ulong)data->src+data->blocks
258 *data->blocksize);
259#endif
260 if (wml_value > WML_WR_WML_MAX)
261 wml_value = WML_WR_WML_MAX_VAL;
262 if (priv->wp_enable) {
263 if ((esdhc_read32(®s->prsstat) &
264 PRSSTAT_WPSPL) == 0) {
265 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
266 return -ETIMEDOUT;
267 }
268 }
269
270 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
271 wml_value << 16);
272#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
273#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
274 addr = virt_to_phys((void *)(data->src));
275 if (upper_32_bits(addr))
276 printf("Error found for upper 32 bits\n");
277 else
278 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
279#else
280 esdhc_write32(®s->dsaddr, (u32)data->src);
281#endif
282#endif
283 }
284
285 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
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309 timeout = fls(mmc->clock/2);
310 timeout -= 13;
311
312 if (timeout > 14)
313 timeout = 14;
314
315 if (timeout < 0)
316 timeout = 0;
317
318#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
319 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
320 timeout++;
321#endif
322
323#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
324 timeout = 0xE;
325#endif
326 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
327
328 return 0;
329}
330
331static void check_and_invalidate_dcache_range
332 (struct mmc_cmd *cmd,
333 struct mmc_data *data) {
334 unsigned start = 0;
335 unsigned end = 0;
336 unsigned size = roundup(ARCH_DMA_MINALIGN,
337 data->blocks*data->blocksize);
338#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
339 dma_addr_t addr;
340
341 addr = virt_to_phys((void *)(data->dest));
342 if (upper_32_bits(addr))
343 printf("Error found for upper 32 bits\n");
344 else
345 start = lower_32_bits(addr);
346#else
347 start = (unsigned)data->dest;
348#endif
349 end = start + size;
350 invalidate_dcache_range(start, end);
351}
352
353
354
355
356
357static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
358 struct mmc_cmd *cmd, struct mmc_data *data)
359{
360 int err = 0;
361 uint xfertyp;
362 uint irqstat;
363 struct fsl_esdhc *regs = priv->esdhc_regs;
364
365#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
366 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
367 return 0;
368#endif
369
370 esdhc_write32(®s->irqstat, -1);
371
372 sync();
373
374
375 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
376 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
377 ;
378
379 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
380 ;
381
382
383
384
385
386
387 udelay(1000);
388
389
390 if (data) {
391 err = esdhc_setup_data(priv, mmc, data);
392 if(err)
393 return err;
394
395 if (data->flags & MMC_DATA_READ)
396 check_and_invalidate_dcache_range(cmd, data);
397 }
398
399
400 xfertyp = esdhc_xfertyp(cmd, data);
401
402
403 esdhc_write32(®s->irqsigen, 0);
404
405
406 esdhc_write32(®s->cmdarg, cmd->cmdarg);
407#if defined(CONFIG_FSL_USDHC)
408 esdhc_write32(®s->mixctrl,
409 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
410 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
411 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
412#else
413 esdhc_write32(®s->xfertyp, xfertyp);
414#endif
415
416
417 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
418 ;
419
420 irqstat = esdhc_read32(®s->irqstat);
421
422 if (irqstat & CMD_ERR) {
423 err = -ECOMM;
424 goto out;
425 }
426
427 if (irqstat & IRQSTAT_CTOE) {
428 err = -ETIMEDOUT;
429 goto out;
430 }
431
432
433 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
434 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
435
436 printf("Run CMD11 1.8V switch\n");
437
438 udelay(5000);
439 }
440
441
442 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
443 int timeout = 6000;
444
445
446 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
447 PRSSTAT_DAT0)) {
448 udelay(100);
449 timeout--;
450 }
451
452 if (timeout <= 0) {
453 printf("Timeout waiting for DAT0 to go high!\n");
454 err = -ETIMEDOUT;
455 goto out;
456 }
457 }
458
459
460 if (cmd->resp_type & MMC_RSP_136) {
461 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
462
463 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
464 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
465 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
466 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
467 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
468 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
469 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
470 cmd->response[3] = (cmdrsp0 << 8);
471 } else
472 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
473
474
475 if (data) {
476#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
477 esdhc_pio_read_write(priv, data);
478#else
479 do {
480 irqstat = esdhc_read32(®s->irqstat);
481
482 if (irqstat & IRQSTAT_DTOE) {
483 err = -ETIMEDOUT;
484 goto out;
485 }
486
487 if (irqstat & DATA_ERR) {
488 err = -ECOMM;
489 goto out;
490 }
491 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
492
493
494
495
496
497
498 if (data->flags & MMC_DATA_READ)
499 check_and_invalidate_dcache_range(cmd, data);
500#endif
501 }
502
503out:
504
505 if (err) {
506 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
507 SYSCTL_RSTC);
508 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
509 ;
510
511 if (data) {
512 esdhc_write32(®s->sysctl,
513 esdhc_read32(®s->sysctl) |
514 SYSCTL_RSTD);
515 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
516 ;
517 }
518
519
520 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
521 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
522 }
523
524 esdhc_write32(®s->irqstat, -1);
525
526 return err;
527}
528
529static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
530{
531 int div = 1;
532#ifdef ARCH_MXC
533 int pre_div = 1;
534#else
535 int pre_div = 2;
536#endif
537 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
538 struct fsl_esdhc *regs = priv->esdhc_regs;
539 int sdhc_clk = priv->sdhc_clk;
540 uint clk;
541
542 if (clock < mmc->cfg->f_min)
543 clock = mmc->cfg->f_min;
544
545 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
546 pre_div *= 2;
547
548 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
549 div++;
550
551 pre_div >>= 1;
552 div -= 1;
553
554 clk = (pre_div << 8) | (div << 4);
555
556#ifdef CONFIG_FSL_USDHC
557 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
558#else
559 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
560#endif
561
562 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
563
564 udelay(10000);
565
566#ifdef CONFIG_FSL_USDHC
567 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
568#else
569 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
570#endif
571
572}
573
574#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
575static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
576{
577 struct fsl_esdhc *regs = priv->esdhc_regs;
578 u32 value;
579 u32 time_out;
580
581 value = esdhc_read32(®s->sysctl);
582
583 if (enable)
584 value |= SYSCTL_CKEN;
585 else
586 value &= ~SYSCTL_CKEN;
587
588 esdhc_write32(®s->sysctl, value);
589
590 time_out = 20;
591 value = PRSSTAT_SDSTB;
592 while (!(esdhc_read32(®s->prsstat) & value)) {
593 if (time_out == 0) {
594 printf("fsl_esdhc: Internal clock never stabilised.\n");
595 break;
596 }
597 time_out--;
598 mdelay(1);
599 }
600}
601#endif
602
603static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
604{
605 struct fsl_esdhc *regs = priv->esdhc_regs;
606
607#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
608
609 esdhc_clock_control(priv, false);
610 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
611 esdhc_clock_control(priv, true);
612#endif
613
614 set_sysctl(priv, mmc, mmc->clock);
615
616
617 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
618
619 if (mmc->bus_width == 4)
620 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
621 else if (mmc->bus_width == 8)
622 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
623
624 return 0;
625}
626
627static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
628{
629 struct fsl_esdhc *regs = priv->esdhc_regs;
630 ulong start;
631
632
633 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
634
635
636 start = get_timer(0);
637 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
638 if (get_timer(start) > 1000)
639 return -ETIMEDOUT;
640 }
641
642#if defined(CONFIG_FSL_USDHC)
643
644 esdhc_write32(®s->mmcboot, 0x0);
645
646 esdhc_write32(®s->mixctrl, 0x0);
647 esdhc_write32(®s->clktunectrlstatus, 0x0);
648
649
650 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
651
652
653 esdhc_write32(®s->dllctrl, 0x0);
654#endif
655
656#ifndef ARCH_MXC
657
658 esdhc_write32(®s->scr, 0x00000040);
659#endif
660
661#ifndef CONFIG_FSL_USDHC
662 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
663#else
664 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
665#endif
666
667
668 mmc_set_clock(mmc, 400000);
669
670
671 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
672
673
674 esdhc_write32(®s->proctl, PROCTL_INIT);
675
676
677 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
678
679 if (priv->vs18_enable)
680 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
681
682 return 0;
683}
684
685static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
686{
687 struct fsl_esdhc *regs = priv->esdhc_regs;
688 int timeout = 1000;
689
690#ifdef CONFIG_ESDHC_DETECT_QUIRK
691 if (CONFIG_ESDHC_DETECT_QUIRK)
692 return 1;
693#endif
694
695#if CONFIG_IS_ENABLED(DM_MMC)
696 if (priv->non_removable)
697 return 1;
698#ifdef CONFIG_DM_GPIO
699 if (dm_gpio_is_valid(&priv->cd_gpio))
700 return dm_gpio_get_value(&priv->cd_gpio);
701#endif
702#endif
703
704 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
705 udelay(1000);
706
707 return timeout > 0;
708}
709
710static int esdhc_reset(struct fsl_esdhc *regs)
711{
712 ulong start;
713
714
715 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
716
717
718 start = get_timer(0);
719 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
720 if (get_timer(start) > 100) {
721 printf("MMC/SD: Reset never completed.\n");
722 return -ETIMEDOUT;
723 }
724 }
725
726 return 0;
727}
728
729#if !CONFIG_IS_ENABLED(DM_MMC)
730static int esdhc_getcd(struct mmc *mmc)
731{
732 struct fsl_esdhc_priv *priv = mmc->priv;
733
734 return esdhc_getcd_common(priv);
735}
736
737static int esdhc_init(struct mmc *mmc)
738{
739 struct fsl_esdhc_priv *priv = mmc->priv;
740
741 return esdhc_init_common(priv, mmc);
742}
743
744static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
745 struct mmc_data *data)
746{
747 struct fsl_esdhc_priv *priv = mmc->priv;
748
749 return esdhc_send_cmd_common(priv, mmc, cmd, data);
750}
751
752static int esdhc_set_ios(struct mmc *mmc)
753{
754 struct fsl_esdhc_priv *priv = mmc->priv;
755
756 return esdhc_set_ios_common(priv, mmc);
757}
758
759static const struct mmc_ops esdhc_ops = {
760 .getcd = esdhc_getcd,
761 .init = esdhc_init,
762 .send_cmd = esdhc_send_cmd,
763 .set_ios = esdhc_set_ios,
764};
765#endif
766
767static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
768 struct fsl_esdhc_plat *plat)
769{
770 struct mmc_config *cfg;
771 struct fsl_esdhc *regs;
772 u32 caps, voltage_caps;
773 int ret;
774
775 if (!priv)
776 return -EINVAL;
777
778 regs = priv->esdhc_regs;
779
780
781 ret = esdhc_reset(regs);
782 if (ret)
783 return ret;
784
785#ifndef CONFIG_FSL_USDHC
786 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
787 | SYSCTL_IPGEN | SYSCTL_CKEN);
788#else
789 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
790 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
791#endif
792
793 if (priv->vs18_enable)
794 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
795
796 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
797 cfg = &plat->cfg;
798#ifndef CONFIG_DM_MMC
799 memset(cfg, '\0', sizeof(*cfg));
800#endif
801
802 voltage_caps = 0;
803 caps = esdhc_read32(®s->hostcapblt);
804
805#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
806 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
807 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
808#endif
809
810
811#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
812 caps = caps | ESDHC_HOSTCAPBLT_VS33;
813#endif
814
815 if (caps & ESDHC_HOSTCAPBLT_VS18)
816 voltage_caps |= MMC_VDD_165_195;
817 if (caps & ESDHC_HOSTCAPBLT_VS30)
818 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
819 if (caps & ESDHC_HOSTCAPBLT_VS33)
820 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
821
822 cfg->name = "FSL_SDHC";
823#if !CONFIG_IS_ENABLED(DM_MMC)
824 cfg->ops = &esdhc_ops;
825#endif
826#ifdef CONFIG_SYS_SD_VOLTAGE
827 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
828#else
829 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
830#endif
831 if ((cfg->voltages & voltage_caps) == 0) {
832 printf("voltage not supported by controller\n");
833 return -1;
834 }
835
836 if (priv->bus_width == 8)
837 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
838 else if (priv->bus_width == 4)
839 cfg->host_caps = MMC_MODE_4BIT;
840
841 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
842#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
843 cfg->host_caps |= MMC_MODE_DDR_52MHz;
844#endif
845
846 if (priv->bus_width > 0) {
847 if (priv->bus_width < 8)
848 cfg->host_caps &= ~MMC_MODE_8BIT;
849 if (priv->bus_width < 4)
850 cfg->host_caps &= ~MMC_MODE_4BIT;
851 }
852
853 if (caps & ESDHC_HOSTCAPBLT_HSS)
854 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
855
856#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
857 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
858 cfg->host_caps &= ~MMC_MODE_8BIT;
859#endif
860
861 cfg->f_min = 400000;
862 cfg->f_max = min(priv->sdhc_clk, (u32)52000000);
863
864 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
865
866 return 0;
867}
868
869#if !CONFIG_IS_ENABLED(DM_MMC)
870static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
871 struct fsl_esdhc_priv *priv)
872{
873 if (!cfg || !priv)
874 return -EINVAL;
875
876 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
877 priv->bus_width = cfg->max_bus_width;
878 priv->sdhc_clk = cfg->sdhc_clk;
879 priv->wp_enable = cfg->wp_enable;
880 priv->vs18_enable = cfg->vs18_enable;
881
882 return 0;
883};
884
885int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
886{
887 struct fsl_esdhc_plat *plat;
888 struct fsl_esdhc_priv *priv;
889 struct mmc *mmc;
890 int ret;
891
892 if (!cfg)
893 return -EINVAL;
894
895 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
896 if (!priv)
897 return -ENOMEM;
898 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
899 if (!plat) {
900 free(priv);
901 return -ENOMEM;
902 }
903
904 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
905 if (ret) {
906 debug("%s xlate failure\n", __func__);
907 free(plat);
908 free(priv);
909 return ret;
910 }
911
912 ret = fsl_esdhc_init(priv, plat);
913 if (ret) {
914 debug("%s init failure\n", __func__);
915 free(plat);
916 free(priv);
917 return ret;
918 }
919
920 mmc = mmc_create(&plat->cfg, priv);
921 if (!mmc)
922 return -EIO;
923
924 priv->mmc = mmc;
925
926 return 0;
927}
928
929int fsl_esdhc_mmc_init(bd_t *bis)
930{
931 struct fsl_esdhc_cfg *cfg;
932
933 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
934 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
935 cfg->sdhc_clk = gd->arch.sdhc_clk;
936 return fsl_esdhc_initialize(bis, cfg);
937}
938#endif
939
940#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
941void mmc_adapter_card_type_ident(void)
942{
943 u8 card_id;
944 u8 value;
945
946 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
947 gd->arch.sdhc_adapter = card_id;
948
949 switch (card_id) {
950 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
951 value = QIXIS_READ(brdcfg[5]);
952 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
953 QIXIS_WRITE(brdcfg[5], value);
954 break;
955 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
956 value = QIXIS_READ(pwr_ctl[1]);
957 value |= QIXIS_EVDD_BY_SDHC_VS;
958 QIXIS_WRITE(pwr_ctl[1], value);
959 break;
960 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
961 value = QIXIS_READ(brdcfg[5]);
962 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
963 QIXIS_WRITE(brdcfg[5], value);
964 break;
965 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
966 break;
967 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
968 break;
969 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
970 break;
971 case QIXIS_ESDHC_NO_ADAPTER:
972 break;
973 default:
974 break;
975 }
976}
977#endif
978
979#ifdef CONFIG_OF_LIBFDT
980__weak int esdhc_status_fixup(void *blob, const char *compat)
981{
982#ifdef CONFIG_FSL_ESDHC_PIN_MUX
983 if (!hwconfig("esdhc")) {
984 do_fixup_by_compat(blob, compat, "status", "disabled",
985 sizeof("disabled"), 1);
986 return 1;
987 }
988#endif
989 return 0;
990}
991
992void fdt_fixup_esdhc(void *blob, bd_t *bd)
993{
994 const char *compat = "fsl,esdhc";
995
996 if (esdhc_status_fixup(blob, compat))
997 return;
998
999#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1000 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1001 gd->arch.sdhc_clk, 1);
1002#else
1003 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1004 gd->arch.sdhc_clk, 1);
1005#endif
1006#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1007 do_fixup_by_compat_u32(blob, compat, "adapter-type",
1008 (u32)(gd->arch.sdhc_adapter), 1);
1009#endif
1010}
1011#endif
1012
1013#if CONFIG_IS_ENABLED(DM_MMC)
1014#include <asm/arch/clock.h>
1015__weak void init_clk_usdhc(u32 index)
1016{
1017}
1018
1019static int fsl_esdhc_probe(struct udevice *dev)
1020{
1021 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1022 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1023 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1024#ifdef CONFIG_DM_REGULATOR
1025 struct udevice *vqmmc_dev;
1026#endif
1027 fdt_addr_t addr;
1028 unsigned int val;
1029 struct mmc *mmc;
1030 int ret;
1031
1032 addr = dev_read_addr(dev);
1033 if (addr == FDT_ADDR_T_NONE)
1034 return -EINVAL;
1035
1036 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1037 priv->dev = dev;
1038
1039 val = dev_read_u32_default(dev, "bus-width", -1);
1040 if (val == 8)
1041 priv->bus_width = 8;
1042 else if (val == 4)
1043 priv->bus_width = 4;
1044 else
1045 priv->bus_width = 1;
1046
1047 if (dev_read_bool(dev, "non-removable")) {
1048 priv->non_removable = 1;
1049 } else {
1050 priv->non_removable = 0;
1051#ifdef CONFIG_DM_GPIO
1052 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1053 GPIOD_IS_IN);
1054#endif
1055 }
1056
1057 priv->wp_enable = 1;
1058
1059#ifdef CONFIG_DM_GPIO
1060 ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1061 GPIOD_IS_IN);
1062 if (ret)
1063 priv->wp_enable = 0;
1064#endif
1065
1066 priv->vs18_enable = 0;
1067
1068#ifdef CONFIG_DM_REGULATOR
1069
1070
1071
1072
1073 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1074 if (ret) {
1075 dev_dbg(dev, "no vqmmc-supply\n");
1076 } else {
1077 ret = regulator_set_enable(vqmmc_dev, true);
1078 if (ret) {
1079 dev_err(dev, "fail to enable vqmmc-supply\n");
1080 return ret;
1081 }
1082
1083 if (regulator_get_value(vqmmc_dev) == 1800000)
1084 priv->vs18_enable = 1;
1085 }
1086#endif
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108 init_clk_usdhc(dev->seq);
1109
1110 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1111 if (priv->sdhc_clk <= 0) {
1112 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1113 return -EINVAL;
1114 }
1115
1116 ret = fsl_esdhc_init(priv, plat);
1117 if (ret) {
1118 dev_err(dev, "fsl_esdhc_init failure\n");
1119 return ret;
1120 }
1121
1122 mmc = &plat->mmc;
1123 mmc->cfg = &plat->cfg;
1124 mmc->dev = dev;
1125 upriv->mmc = mmc;
1126
1127 return esdhc_init_common(priv, mmc);
1128}
1129
1130#if CONFIG_IS_ENABLED(DM_MMC)
1131static int fsl_esdhc_get_cd(struct udevice *dev)
1132{
1133 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1134
1135 return true;
1136 return esdhc_getcd_common(priv);
1137}
1138
1139static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1140 struct mmc_data *data)
1141{
1142 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1143 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1144
1145 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1146}
1147
1148static int fsl_esdhc_set_ios(struct udevice *dev)
1149{
1150 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1151 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1152
1153 return esdhc_set_ios_common(priv, &plat->mmc);
1154}
1155
1156static const struct dm_mmc_ops fsl_esdhc_ops = {
1157 .get_cd = fsl_esdhc_get_cd,
1158 .send_cmd = fsl_esdhc_send_cmd,
1159 .set_ios = fsl_esdhc_set_ios,
1160};
1161#endif
1162
1163static const struct udevice_id fsl_esdhc_ids[] = {
1164 { .compatible = "fsl,imx6ul-usdhc", },
1165 { .compatible = "fsl,imx6sx-usdhc", },
1166 { .compatible = "fsl,imx6sl-usdhc", },
1167 { .compatible = "fsl,imx6q-usdhc", },
1168 { .compatible = "fsl,imx7d-usdhc", },
1169 { .compatible = "fsl,imx7ulp-usdhc", },
1170 { .compatible = "fsl,esdhc", },
1171 { }
1172};
1173
1174#if CONFIG_IS_ENABLED(BLK)
1175static int fsl_esdhc_bind(struct udevice *dev)
1176{
1177 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1178
1179 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1180}
1181#endif
1182
1183U_BOOT_DRIVER(fsl_esdhc) = {
1184 .name = "fsl-esdhc-mmc",
1185 .id = UCLASS_MMC,
1186 .of_match = fsl_esdhc_ids,
1187 .ops = &fsl_esdhc_ops,
1188#if CONFIG_IS_ENABLED(BLK)
1189 .bind = fsl_esdhc_bind,
1190#endif
1191 .probe = fsl_esdhc_probe,
1192 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1193 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
1194};
1195#endif
1196