1/* 2 * Copyright (C) 2013-2014 Altera Corporation <www.altera.com> 3 * Copyright (C) 2009-2010, Intel Corporation and its suppliers. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef __DENALI_H__ 9#define __DENALI_H__ 10 11#include <linux/mtd/nand.h> 12 13#define DEVICE_RESET 0x0 14#define DEVICE_RESET__BANK0 0x0001 15#define DEVICE_RESET__BANK1 0x0002 16#define DEVICE_RESET__BANK2 0x0004 17#define DEVICE_RESET__BANK3 0x0008 18 19#define TRANSFER_SPARE_REG 0x10 20#define TRANSFER_SPARE_REG__FLAG 0x0001 21 22#define LOAD_WAIT_CNT 0x20 23#define LOAD_WAIT_CNT__VALUE 0xffff 24 25#define PROGRAM_WAIT_CNT 0x30 26#define PROGRAM_WAIT_CNT__VALUE 0xffff 27 28#define ERASE_WAIT_CNT 0x40 29#define ERASE_WAIT_CNT__VALUE 0xffff 30 31#define INT_MON_CYCCNT 0x50 32#define INT_MON_CYCCNT__VALUE 0xffff 33 34#define RB_PIN_ENABLED 0x60 35#define RB_PIN_ENABLED__BANK0 0x0001 36#define RB_PIN_ENABLED__BANK1 0x0002 37#define RB_PIN_ENABLED__BANK2 0x0004 38#define RB_PIN_ENABLED__BANK3 0x0008 39 40#define MULTIPLANE_OPERATION 0x70 41#define MULTIPLANE_OPERATION__FLAG 0x0001 42 43#define MULTIPLANE_READ_ENABLE 0x80 44#define MULTIPLANE_READ_ENABLE__FLAG 0x0001 45 46#define COPYBACK_DISABLE 0x90 47#define COPYBACK_DISABLE__FLAG 0x0001 48 49#define CACHE_WRITE_ENABLE 0xa0 50#define CACHE_WRITE_ENABLE__FLAG 0x0001 51 52#define CACHE_READ_ENABLE 0xb0 53#define CACHE_READ_ENABLE__FLAG 0x0001 54 55#define PREFETCH_MODE 0xc0 56#define PREFETCH_MODE__PREFETCH_EN 0x0001 57#define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0 58 59#define CHIP_ENABLE_DONT_CARE 0xd0 60#define CHIP_EN_DONT_CARE__FLAG 0x01 61 62#define ECC_ENABLE 0xe0 63#define ECC_ENABLE__FLAG 0x0001 64 65#define GLOBAL_INT_ENABLE 0xf0 66#define GLOBAL_INT_EN_FLAG 0x01 67 68#define WE_2_RE 0x100 69#define WE_2_RE__VALUE 0x003f 70 71#define ADDR_2_DATA 0x110 72#define ADDR_2_DATA__VALUE 0x003f 73 74#define RE_2_WE 0x120 75#define RE_2_WE__VALUE 0x003f 76 77#define ACC_CLKS 0x130 78#define ACC_CLKS__VALUE 0x000f 79 80#define NUMBER_OF_PLANES 0x140 81#define NUMBER_OF_PLANES__VALUE 0x0007 82 83#define PAGES_PER_BLOCK 0x150 84#define PAGES_PER_BLOCK__VALUE 0xffff 85 86#define DEVICE_WIDTH 0x160 87#define DEVICE_WIDTH__VALUE 0x0003 88 89#define DEVICE_MAIN_AREA_SIZE 0x170 90#define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff 91 92#define DEVICE_SPARE_AREA_SIZE 0x180 93#define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff 94 95#define TWO_ROW_ADDR_CYCLES 0x190 96#define TWO_ROW_ADDR_CYCLES__FLAG 0x0001 97 98#define MULTIPLANE_ADDR_RESTRICT 0x1a0 99#define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001 100 101#define ECC_CORRECTION 0x1b0 102#define ECC_CORRECTION__VALUE 0x001f 103 104#define READ_MODE 0x1c0 105#define READ_MODE__VALUE 0x000f 106 107#define WRITE_MODE 0x1d0 108#define WRITE_MODE__VALUE 0x000f 109 110#define COPYBACK_MODE 0x1e0 111#define COPYBACK_MODE__VALUE 0x000f 112 113#define RDWR_EN_LO_CNT 0x1f0 114#define RDWR_EN_LO_CNT__VALUE 0x001f 115 116#define RDWR_EN_HI_CNT 0x200 117#define RDWR_EN_HI_CNT__VALUE 0x001f 118 119#define MAX_RD_DELAY 0x210 120#define MAX_RD_DELAY__VALUE 0x000f 121 122#define CS_SETUP_CNT 0x220 123#define CS_SETUP_CNT__VALUE 0x001f 124 125#define SPARE_AREA_SKIP_BYTES 0x230 126#define SPARE_AREA_SKIP_BYTES__VALUE 0x003f 127 128#define SPARE_AREA_MARKER 0x240 129#define SPARE_AREA_MARKER__VALUE 0xffff 130 131#define DEVICES_CONNECTED 0x250 132#define DEVICES_CONNECTED__VALUE 0x0007 133 134#define DIE_MASK 0x260 135#define DIE_MASK__VALUE 0x00ff 136 137#define FIRST_BLOCK_OF_NEXT_PLANE 0x270 138#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff 139 140#define WRITE_PROTECT 0x280 141#define WRITE_PROTECT__FLAG 0x0001 142 143#define RE_2_RE 0x290 144#define RE_2_RE__VALUE 0x003f 145 146#define MANUFACTURER_ID 0x300 147#define MANUFACTURER_ID__VALUE 0x00ff 148 149#define DEVICE_ID 0x310 150#define DEVICE_ID__VALUE 0x00ff 151 152#define DEVICE_PARAM_0 0x320 153#define DEVICE_PARAM_0__VALUE 0x00ff 154 155#define DEVICE_PARAM_1 0x330 156#define DEVICE_PARAM_1__VALUE 0x00ff 157 158#define DEVICE_PARAM_2 0x340 159#define DEVICE_PARAM_2__VALUE 0x00ff 160 161#define LOGICAL_PAGE_DATA_SIZE 0x350 162#define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff 163 164#define LOGICAL_PAGE_SPARE_SIZE 0x360 165#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff 166 167#define REVISION 0x370 168#define REVISION__VALUE 0xffff 169 170#define ONFI_DEVICE_FEATURES 0x380 171#define ONFI_DEVICE_FEATURES__VALUE 0x003f 172 173#define ONFI_OPTIONAL_COMMANDS 0x390 174#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f 175 176#define ONFI_TIMING_MODE 0x3a0 177#define ONFI_TIMING_MODE__VALUE 0x003f 178 179#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0 180#define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f 181 182#define ONFI_DEVICE_NO_OF_LUNS 0x3c0 183#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff 184#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100 185 186#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0 187#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff 188 189#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0 190#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff 191 192#define FEATURES 0x3f0 193#define FEATURES__N_BANKS 0x0003 194#define FEATURES__ECC_MAX_ERR 0x003c 195#define FEATURES__DMA 0x0040 196#define FEATURES__CMD_DMA 0x0080 197#define FEATURES__PARTITION 0x0100 198#define FEATURES__XDMA_SIDEBAND 0x0200 199#define FEATURES__GPREG 0x0400 200#define FEATURES__INDEX_ADDR 0x0800 201 202#define TRANSFER_MODE 0x400 203#define TRANSFER_MODE__VALUE 0x0003 204 205#define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50)) 206#define INTR_EN(__bank) (0x420 + ((__bank) * 0x50)) 207 208/* 209 * Some versions of the IP have the ECC fixup handled in hardware. In this 210 * configuration we only get interrupted when the error is uncorrectable. 211 * Unfortunately this bit replaces INTR_STATUS__ECC_TRANSACTION_DONE from the 212 * old IP. 213 */ 214#define INTR_STATUS__ECC_UNCOR_ERR 0x0001 215#define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001 216#define INTR_STATUS__ECC_ERR 0x0002 217#define INTR_STATUS__DMA_CMD_COMP 0x0004 218#define INTR_STATUS__TIME_OUT 0x0008 219#define INTR_STATUS__PROGRAM_FAIL 0x0010 220#define INTR_STATUS__ERASE_FAIL 0x0020 221#define INTR_STATUS__LOAD_COMP 0x0040 222#define INTR_STATUS__PROGRAM_COMP 0x0080 223#define INTR_STATUS__ERASE_COMP 0x0100 224#define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200 225#define INTR_STATUS__LOCKED_BLK 0x0400 226#define INTR_STATUS__UNSUP_CMD 0x0800 227#define INTR_STATUS__INT_ACT 0x1000 228#define INTR_STATUS__RST_COMP 0x2000 229#define INTR_STATUS__PIPE_CMD_ERR 0x4000 230#define INTR_STATUS__PAGE_XFER_INC 0x8000 231 232#define INTR_EN__ECC_TRANSACTION_DONE 0x0001 233#define INTR_EN__ECC_ERR 0x0002 234#define INTR_EN__DMA_CMD_COMP 0x0004 235#define INTR_EN__TIME_OUT 0x0008 236#define INTR_EN__PROGRAM_FAIL 0x0010 237#define INTR_EN__ERASE_FAIL 0x0020 238#define INTR_EN__LOAD_COMP 0x0040 239#define INTR_EN__PROGRAM_COMP 0x0080 240#define INTR_EN__ERASE_COMP 0x0100 241#define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200 242#define INTR_EN__LOCKED_BLK 0x0400 243#define INTR_EN__UNSUP_CMD 0x0800 244#define INTR_EN__INT_ACT 0x1000 245#define INTR_EN__RST_COMP 0x2000 246#define INTR_EN__PIPE_CMD_ERR 0x4000 247#define INTR_EN__PAGE_XFER_INC 0x8000 248 249#define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50)) 250#define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50)) 251#define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50)) 252 253#define DATA_INTR 0x550 254#define DATA_INTR__WRITE_SPACE_AV 0x0001 255#define DATA_INTR__READ_DATA_AV 0x0002 256 257#define DATA_INTR_EN 0x560 258#define DATA_INTR_EN__WRITE_SPACE_AV 0x0001 259#define DATA_INTR_EN__READ_DATA_AV 0x0002 260 261#define GPREG_0 0x570 262#define GPREG_0__VALUE 0xffff 263 264#define GPREG_1 0x580 265#define GPREG_1__VALUE 0xffff 266 267#define GPREG_2 0x590 268#define GPREG_2__VALUE 0xffff 269 270#define GPREG_3 0x5a0 271#define GPREG_3__VALUE 0xffff 272 273#define ECC_THRESHOLD 0x600 274#define ECC_THRESHOLD__VALUE 0x03ff 275 276#define ECC_ERROR_BLOCK_ADDRESS 0x610 277#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff 278 279#define ECC_ERROR_PAGE_ADDRESS 0x620 280#define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff 281#define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000 282 283#define ECC_ERROR_ADDRESS 0x630 284#define ECC_ERROR_ADDRESS__OFFSET 0x0fff 285#define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000 286 287#define ERR_CORRECTION_INFO 0x640 288#define ERR_CORRECTION_INFO__BYTEMASK 0x00ff 289#define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00 290#define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000 291#define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000 292 293#define DMA_ENABLE 0x700 294#define DMA_ENABLE__FLAG 0x0001 295 296#define IGNORE_ECC_DONE 0x710 297#define IGNORE_ECC_DONE__FLAG 0x0001 298 299#define DMA_INTR 0x720 300#define DMA_INTR__TARGET_ERROR 0x0001 301#define DMA_INTR__DESC_COMP_CHANNEL0 0x0002 302#define DMA_INTR__DESC_COMP_CHANNEL1 0x0004 303#define DMA_INTR__DESC_COMP_CHANNEL2 0x0008 304#define DMA_INTR__DESC_COMP_CHANNEL3 0x0010 305#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020 306 307#define DMA_INTR_EN 0x730 308#define DMA_INTR_EN__TARGET_ERROR 0x0001 309#define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002 310#define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004 311#define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008 312#define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010 313#define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020 314 315#define TARGET_ERR_ADDR_LO 0x740 316#define TARGET_ERR_ADDR_LO__VALUE 0xffff 317 318#define TARGET_ERR_ADDR_HI 0x750 319#define TARGET_ERR_ADDR_HI__VALUE 0xffff 320 321#define CHNL_ACTIVE 0x760 322#define CHNL_ACTIVE__CHANNEL0 0x0001 323#define CHNL_ACTIVE__CHANNEL1 0x0002 324#define CHNL_ACTIVE__CHANNEL2 0x0004 325#define CHNL_ACTIVE__CHANNEL3 0x0008 326 327#define ACTIVE_SRC_ID 0x800 328#define ACTIVE_SRC_ID__VALUE 0x00ff 329 330#define PTN_INTR 0x810 331#define PTN_INTR__CONFIG_ERROR 0x0001 332#define PTN_INTR__ACCESS_ERROR_BANK0 0x0002 333#define PTN_INTR__ACCESS_ERROR_BANK1 0x0004 334#define PTN_INTR__ACCESS_ERROR_BANK2 0x0008 335#define PTN_INTR__ACCESS_ERROR_BANK3 0x0010 336#define PTN_INTR__REG_ACCESS_ERROR 0x0020 337 338#define PTN_INTR_EN 0x820 339#define PTN_INTR_EN__CONFIG_ERROR 0x0001 340#define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002 341#define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004 342#define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008 343#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010 344#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 345 346#define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40)) 347#define PERM_SRC_ID__SRCID 0x00ff 348#define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800 349#define PERM_SRC_ID__WRITE_ACTIVE 0x2000 350#define PERM_SRC_ID__READ_ACTIVE 0x4000 351#define PERM_SRC_ID__PARTITION_VALID 0x8000 352 353#define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40)) 354#define MIN_BLK_ADDR__VALUE 0xffff 355 356#define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40)) 357#define MAX_BLK_ADDR__VALUE 0xffff 358 359#define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40)) 360#define MIN_MAX_BANK__MIN_VALUE 0x0003 361#define MIN_MAX_BANK__MAX_VALUE 0x000c 362 363/* lld.h */ 364#define GOOD_BLOCK 0 365#define DEFECTIVE_BLOCK 1 366#define READ_ERROR 2 367 368#define CLK_X 5 369#define CLK_MULTI 4 370 371/* spectraswconfig.h */ 372#define CMD_DMA 0 373 374#define SPECTRA_PARTITION_ID 0 375/**** Block Table and Reserved Block Parameters *****/ 376#define SPECTRA_START_BLOCK 3 377#define NUM_FREE_BLOCKS_GATE 30 378 379/* KBV - Updated to LNW scratch register address */ 380#define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR 381#define SCRATCH_REG_SIZE 64 382 383#define GLOB_HWCTL_DEFAULT_BLKS 2048 384 385#define CUSTOM_CONF_PARAMS 0 386 387#define INDEX_CTRL_REG 0x0 388#define INDEX_DATA_REG 0x10 389 390#define MODE_00 0x00000000 391#define MODE_01 0x04000000 392#define MODE_10 0x08000000 393#define MODE_11 0x0C000000 394 395 396#define DATA_TRANSFER_MODE 0 397#define PROTECTION_PER_BLOCK 1 398#define LOAD_WAIT_COUNT 2 399#define PROGRAM_WAIT_COUNT 3 400#define ERASE_WAIT_COUNT 4 401#define INT_MONITOR_CYCLE_COUNT 5 402#define READ_BUSY_PIN_ENABLED 6 403#define MULTIPLANE_OPERATION_SUPPORT 7 404#define PRE_FETCH_MODE 8 405#define CE_DONT_CARE_SUPPORT 9 406#define COPYBACK_SUPPORT 10 407#define CACHE_WRITE_SUPPORT 11 408#define CACHE_READ_SUPPORT 12 409#define NUM_PAGES_IN_BLOCK 13 410#define ECC_ENABLE_SELECT 14 411#define WRITE_ENABLE_2_READ_ENABLE 15 412#define ADDRESS_2_DATA 16 413#define READ_ENABLE_2_WRITE_ENABLE 17 414#define TWO_ROW_ADDRESS_CYCLES 18 415#define MULTIPLANE_ADDRESS_RESTRICT 19 416#define ACC_CLOCKS 20 417#define READ_WRITE_ENABLE_LOW_COUNT 21 418#define READ_WRITE_ENABLE_HIGH_COUNT 22 419 420#define ECC_SECTOR_SIZE 512 421 422#define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) 423 424struct nand_buf { 425 int head; 426 int tail; 427 /* seprating dma_buf as buf can be used for status read purpose */ 428 uint8_t dma_buf[DENALI_BUF_SIZE] __aligned(64); 429 uint8_t buf[DENALI_BUF_SIZE]; 430}; 431 432#define INTEL_CE4100 1 433#define INTEL_MRST 2 434#define DT 3 435 436struct denali_nand_info { 437 struct nand_chip nand; 438 unsigned long clk_x_rate; /* bus interface clock rate */ 439 int flash_bank; /* currently selected chip */ 440 int status; 441 int platform; 442 struct nand_buf buf; 443 struct device *dev; 444 int total_used_banks; 445 uint32_t block; /* stored for future use */ 446 uint32_t page; 447 void __iomem *flash_reg; /* Mapped io reg base address */ 448 void __iomem *flash_mem; /* Mapped io reg base address */ 449 450 /* elements used by ISR */ 451 /*struct completion complete;*/ 452 453 uint32_t irq_status; 454 int irq_debug_array[32]; 455 int idx; 456 int irq; 457 458 uint32_t devnum; /* represent how many nands connected */ 459 uint32_t fwblks; /* represent how many blocks FW used */ 460 uint32_t totalblks; 461 uint32_t blksperchip; 462 uint32_t bbtskipbytes; 463 uint32_t max_banks; 464 unsigned int revision; 465 unsigned int caps; 466}; 467 468#define DENALI_CAP_HW_ECC_FIXUP BIT(0) 469#define DENALI_CAP_DMA_64BIT BIT(1) 470 471int denali_init(struct denali_nand_info *denali); 472 473#endif /* __DENALI_H__ */ 474