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8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
13#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
14#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
15#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
16#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
17
18#ifndef CONFIG_SYS_TEXT_BASE
19#define CONFIG_SYS_TEXT_BASE 0xFE000000
20#endif
21
22#ifndef CONFIG_SYS_MONITOR_BASE
23#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
24#endif
25
26
27
28
29#define CONFIG_E300 1
30#define CONFIG_MPC831x 1
31#define CONFIG_MPC8315 1
32#define CONFIG_MPC8315ERDB 1
33
34
35
36
37#define CONFIG_83XX_CLKIN 66666667
38#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
39
40
41
42
43
44
45#define CONFIG_SYS_HRCW_LOW (\
46 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
47 HRCWL_DDR_TO_SCB_CLK_2X1 |\
48 HRCWL_SVCOD_DIV_2 |\
49 HRCWL_CSB_TO_CLKIN_2X1 |\
50 HRCWL_CORE_TO_CSB_3X1)
51#define CONFIG_SYS_HRCW_HIGH_BASE (\
52 HRCWH_PCI_HOST |\
53 HRCWH_PCI1_ARBITER_ENABLE |\
54 HRCWH_CORE_ENABLE |\
55 HRCWH_BOOTSEQ_DISABLE |\
56 HRCWH_SW_WATCHDOG_DISABLE |\
57 HRCWH_TSEC1M_IN_RGMII |\
58 HRCWH_TSEC2M_IN_RGMII |\
59 HRCWH_BIG_ENDIAN |\
60 HRCWH_LALE_NORMAL)
61
62#ifdef CONFIG_NAND_SPL
63#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
64 HRCWH_FROM_0XFFF00100 |\
65 HRCWH_ROM_LOC_NAND_SP_8BIT |\
66 HRCWH_RL_EXT_NAND)
67#else
68#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
69 HRCWH_FROM_0X00000100 |\
70 HRCWH_ROM_LOC_LOCAL_16BIT |\
71 HRCWH_RL_EXT_LEGACY)
72#endif
73
74
75
76
77#define CONFIG_SYS_SICRH 0x00000000
78#define CONFIG_SYS_SICRL 0x00000000
79
80#define CONFIG_HWCONFIG
81
82
83
84
85#define CONFIG_SYS_IMMR 0xE0000000
86
87
88
89
90#define CONFIG_SYS_ACR_PIPE_DEP 3
91#define CONFIG_SYS_ACR_RPTCNT 3
92#define CONFIG_SYS_SPCR_TSECEP 3
93
94
95
96
97#define CONFIG_SYS_DDR_BASE 0x00000000
98#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
99#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
100#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
101#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
102 | DDRCDR_PZ_LOZ \
103 | DDRCDR_NZ_LOZ \
104 | DDRCDR_ODT \
105 | DDRCDR_Q_DRN)
106
107
108
109
110
111#define CONFIG_SYS_DDR_SIZE 128
112#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
113#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
114 | CSCONFIG_ODT_RD_NEVER \
115 | CSCONFIG_ODT_WR_ONLY_CURRENT \
116 | CSCONFIG_ROW_BIT_13 \
117 | CSCONFIG_COL_BIT_10)
118
119#define CONFIG_SYS_DDR_TIMING_3 0x00000000
120#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
121 | (0 << TIMING_CFG0_WRT_SHIFT) \
122 | (0 << TIMING_CFG0_RRT_SHIFT) \
123 | (0 << TIMING_CFG0_WWT_SHIFT) \
124 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
125 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
126 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
127 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
128
129#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
130 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
131 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
132 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
133 | (6 << TIMING_CFG1_REFREC_SHIFT) \
134 | (2 << TIMING_CFG1_WRREC_SHIFT) \
135 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
136 | (2 << TIMING_CFG1_WRTORD_SHIFT))
137
138#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
139 | (4 << TIMING_CFG2_CPO_SHIFT) \
140 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
141 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
142 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
143 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
144 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
145
146#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
147 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
148
149#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
150 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
151 | SDRAM_CFG_DBW_32)
152
153#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
154#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
155 | (0x0232 << SDRAM_MODE_SD_SHIFT))
156
157#define CONFIG_SYS_DDR_MODE2 0x00000000
158
159
160
161
162#undef CONFIG_SYS_DRAM_TEST
163#define CONFIG_SYS_MEMTEST_START 0x00040000
164#define CONFIG_SYS_MEMTEST_END 0x00140000
165
166
167
168
169#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
170#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
171
172
173
174
175#define CONFIG_SYS_INIT_RAM_LOCK 1
176#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
177#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
178#define CONFIG_SYS_GBL_DATA_OFFSET \
179 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
180
181
182
183
184#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
185#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
186#define CONFIG_SYS_LBC_LBCR 0x00040000
187#define CONFIG_FSL_ELBC 1
188
189
190
191
192#define CONFIG_SYS_FLASH_CFI
193#define CONFIG_FLASH_CFI_DRIVER
194#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
195
196#define CONFIG_SYS_FLASH_BASE 0xFE000000
197#define CONFIG_SYS_FLASH_SIZE 8
198#define CONFIG_SYS_FLASH_PROTECTION 1
199
200
201#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
202#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
203
204#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
205 | BR_PS_16 \
206 | BR_MS_GPCM \
207 | BR_V)
208#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
209 | OR_UPM_XAM \
210 | OR_GPCM_CSNT \
211 | OR_GPCM_ACS_DIV2 \
212 | OR_GPCM_XACS \
213 | OR_GPCM_SCY_15 \
214 | OR_GPCM_TRLX_SET \
215 | OR_GPCM_EHTR_SET \
216 | OR_GPCM_EAD)
217
218#define CONFIG_SYS_MAX_FLASH_BANKS 1
219
220#define CONFIG_SYS_MAX_FLASH_SECT 135
221
222#undef CONFIG_SYS_FLASH_CHECKSUM
223#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
224#define CONFIG_SYS_FLASH_WRITE_TOUT 500
225
226
227
228
229
230#ifdef CONFIG_NAND_SPL
231#define CONFIG_SYS_NAND_BASE 0xFFF00000
232#else
233#define CONFIG_SYS_NAND_BASE 0xE0600000
234#endif
235
236#define CONFIG_MTD_DEVICE
237#define CONFIG_MTD_PARTITION
238
239#define CONFIG_SYS_MAX_NAND_DEVICE 1
240#define CONFIG_NAND_FSL_ELBC 1
241#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
242#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
243
244#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
245#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
246#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
247#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
248#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
249
250#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
251 | BR_DECC_CHK_GEN \
252 | BR_PS_8 \
253 | BR_MS_FCM \
254 | BR_V)
255#define CONFIG_SYS_NAND_OR_PRELIM \
256 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
257 | OR_FCM_CSCT \
258 | OR_FCM_CST \
259 | OR_FCM_CHT \
260 | OR_FCM_SCY_1 \
261 | OR_FCM_TRLX \
262 | OR_FCM_EHTR)
263
264
265#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
266#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
267#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
268#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
269
270#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
271#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
272
273#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
274#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
275
276#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
277 !defined(CONFIG_NAND_SPL)
278#define CONFIG_SYS_RAMBOOT
279#else
280#undef CONFIG_SYS_RAMBOOT
281#endif
282
283
284
285
286#define CONFIG_CONS_INDEX 1
287#define CONFIG_SYS_NS16550_SERIAL
288#define CONFIG_SYS_NS16550_REG_SIZE 1
289#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
290
291#define CONFIG_SYS_BAUDRATE_TABLE \
292 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
293
294#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
295#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
296
297
298#define CONFIG_SYS_I2C
299#define CONFIG_SYS_I2C_FSL
300#define CONFIG_SYS_FSL_I2C_SPEED 400000
301#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
302#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
303#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
304
305
306
307
308#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
309
310
311
312
313#define CONFIG_RTC_DS1337
314#define CONFIG_SYS_I2C_RTC_ADDR 0x68
315
316
317
318
319
320#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
321#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
322#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
323#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
324#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
325#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000
326#define CONFIG_SYS_PCI_IO_BASE 0x00000000
327#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
328#define CONFIG_SYS_PCI_IO_SIZE 0x100000
329
330#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
331#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
332#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
333
334#define CONFIG_SYS_PCIE1_BASE 0xA0000000
335#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
336#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
337#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
338#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
339#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
340#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
341#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
342#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
343
344#define CONFIG_SYS_PCIE2_BASE 0xC0000000
345#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
346#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
347#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
348#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
349#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
350#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
351#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
352#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
353
354#define CONFIG_PCI_INDIRECT_BRIDGE
355#define CONFIG_PCIE
356
357#define CONFIG_EEPRO100
358#undef CONFIG_PCI_SCAN_SHOW
359#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
360
361#define CONFIG_HAS_FSL_DR_USB
362#define CONFIG_SYS_SCCR_USBDRCM 3
363
364#define CONFIG_USB_EHCI_FSL
365#define CONFIG_USB_PHY_TYPE "utmi"
366#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
367
368
369
370
371#define CONFIG_TSEC_ENET
372#define CONFIG_SYS_TSEC1_OFFSET 0x24000
373#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
374#define CONFIG_SYS_TSEC2_OFFSET 0x25000
375#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
376
377
378
379
380#define CONFIG_MII 1
381#define CONFIG_TSEC1 1
382#define CONFIG_TSEC1_NAME "eTSEC0"
383#define CONFIG_TSEC2 1
384#define CONFIG_TSEC2_NAME "eTSEC1"
385#define TSEC1_PHY_ADDR 0
386#define TSEC2_PHY_ADDR 1
387#define TSEC1_PHYIDX 0
388#define TSEC2_PHYIDX 0
389#define TSEC1_FLAGS TSEC_GIGABIT
390#define TSEC2_FLAGS TSEC_GIGABIT
391
392
393#define CONFIG_ETHPRIME "eTSEC1"
394
395
396
397
398#define CONFIG_LIBATA
399#define CONFIG_FSL_SATA
400
401#define CONFIG_SYS_SATA_MAX_DEVICE 2
402#define CONFIG_SATA1
403#define CONFIG_SYS_SATA1_OFFSET 0x18000
404#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
405#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
406#define CONFIG_SATA2
407#define CONFIG_SYS_SATA2_OFFSET 0x19000
408#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
409#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
410
411#ifdef CONFIG_FSL_SATA
412#define CONFIG_LBA48
413#endif
414
415
416
417
418#if !defined(CONFIG_SYS_RAMBOOT)
419 #define CONFIG_ENV_ADDR \
420 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
421 #define CONFIG_ENV_SECT_SIZE 0x10000
422 #define CONFIG_ENV_SIZE 0x2000
423#else
424 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
425 #define CONFIG_ENV_SIZE 0x2000
426#endif
427
428#define CONFIG_LOADS_ECHO 1
429#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
430
431
432
433
434#define CONFIG_BOOTP_BOOTFILESIZE
435#define CONFIG_BOOTP_BOOTPATH
436#define CONFIG_BOOTP_GATEWAY
437#define CONFIG_BOOTP_HOSTNAME
438
439
440
441
442
443#define CONFIG_CMDLINE_EDITING 1
444#define CONFIG_AUTO_COMPLETE
445
446#undef CONFIG_WATCHDOG
447
448
449
450
451#define CONFIG_SYS_LONGHELP
452#define CONFIG_SYS_LOAD_ADDR 0x2000000
453
454
455
456
457
458
459#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
460#define CONFIG_SYS_BOOTM_LEN (64 << 20)
461
462
463
464
465#define CONFIG_SYS_HID0_INIT 0x000000000
466#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
467 HID0_ENABLE_INSTRUCTION_CACHE | \
468 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
469#define CONFIG_SYS_HID2 HID2_HBE
470
471
472
473
474#define CONFIG_HIGH_BATS 1
475
476
477#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
478 | BATL_PP_RW \
479 | BATL_MEMCOHERENCE)
480#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
481 | BATU_BL_128M \
482 | BATU_VS \
483 | BATU_VP)
484#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
485#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
486
487
488#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
489 | BATL_PP_RW \
490 | BATL_CACHEINHIBIT \
491 | BATL_GUARDEDSTORAGE)
492#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
493 | BATU_BL_8M \
494 | BATU_VS \
495 | BATU_VP)
496#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
497#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
498
499
500#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
501 | BATL_PP_RW \
502 | BATL_MEMCOHERENCE)
503#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
504 | BATU_BL_32M \
505 | BATU_VS \
506 | BATU_VP)
507#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
508 | BATL_PP_RW \
509 | BATL_CACHEINHIBIT \
510 | BATL_GUARDEDSTORAGE)
511#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
512
513
514#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
515#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
516 | BATU_BL_128K \
517 | BATU_VS \
518 | BATU_VP)
519#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
520#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
521
522
523#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
524 | BATL_PP_RW \
525 | BATL_MEMCOHERENCE)
526#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
527 | BATU_BL_256M \
528 | BATU_VS \
529 | BATU_VP)
530#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
531#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
532
533
534#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
535 | BATL_PP_RW \
536 | BATL_CACHEINHIBIT \
537 | BATL_GUARDEDSTORAGE)
538#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
539 | BATU_BL_256M \
540 | BATU_VS \
541 | BATU_VP)
542#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
543#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
544
545#define CONFIG_SYS_IBAT6L 0
546#define CONFIG_SYS_IBAT6U 0
547#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
548#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
549
550#define CONFIG_SYS_IBAT7L 0
551#define CONFIG_SYS_IBAT7U 0
552#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
553#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
554
555#if defined(CONFIG_CMD_KGDB)
556#define CONFIG_KGDB_BAUDRATE 230400
557#endif
558
559
560
561
562
563#define CONFIG_ENV_OVERWRITE
564
565#if defined(CONFIG_TSEC_ENET)
566#define CONFIG_HAS_ETH0
567#define CONFIG_HAS_ETH1
568#endif
569
570#define CONFIG_LOADADDR 800000
571
572#define CONFIG_EXTRA_ENV_SETTINGS \
573 "netdev=eth0\0" \
574 "consoledev=ttyS0\0" \
575 "ramdiskaddr=1000000\0" \
576 "ramdiskfile=ramfs.83xx\0" \
577 "fdtaddr=780000\0" \
578 "fdtfile=mpc8315erdb.dtb\0" \
579 "usb_phy_type=utmi\0" \
580 ""
581
582#define CONFIG_NFSBOOTCOMMAND \
583 "setenv bootargs root=/dev/nfs rw " \
584 "nfsroot=$serverip:$rootpath " \
585 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
586 "$netdev:off " \
587 "console=$consoledev,$baudrate $othbootargs;" \
588 "tftp $loadaddr $bootfile;" \
589 "tftp $fdtaddr $fdtfile;" \
590 "bootm $loadaddr - $fdtaddr"
591
592#define CONFIG_RAMBOOTCOMMAND \
593 "setenv bootargs root=/dev/ram rw " \
594 "console=$consoledev,$baudrate $othbootargs;" \
595 "tftp $ramdiskaddr $ramdiskfile;" \
596 "tftp $loadaddr $bootfile;" \
597 "tftp $fdtaddr $fdtfile;" \
598 "bootm $loadaddr $ramdiskaddr $fdtaddr"
599
600#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
601
602#endif
603