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39
40#ifndef __CONFIG_H
41#define __CONFIG_H
42
43#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
44#define CONFIG_SYS_LOWBOOT
45#endif
46
47
48
49
50#define CONFIG_MPC834x
51#define CONFIG_MPC8349
52
53#ifndef CONFIG_SYS_TEXT_BASE
54#define CONFIG_SYS_TEXT_BASE 0xFEF00000
55#endif
56
57#define CONFIG_SYS_IMMR 0xE0000000
58
59#define CONFIG_MISC_INIT_F
60#define CONFIG_MISC_INIT_R
61
62
63
64
65
66#ifdef CONFIG_MPC8349ITX
67
68#define CONFIG_COMPACT_FLASH
69#define CONFIG_VSC7385_ENET
70#define CONFIG_SATA_SIL3114
71#define CONFIG_SYS_USB_HOST
72#endif
73
74#define CONFIG_RTC_DS1337
75#define CONFIG_SYS_I2C
76#define CONFIG_TSEC_ENET
77
78
79
80
81
82
83#ifdef CONFIG_SYS_I2C
84#define CONFIG_SYS_I2C_FSL
85#define CONFIG_SYS_FSL_I2C_SPEED 400000
86#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
87#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
88#define CONFIG_SYS_FSL_I2C2_SPEED 400000
89#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
90#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
91
92#define CONFIG_SYS_SPD_BUS_NUM 1
93#define CONFIG_SYS_RTC_BUS_NUM 1
94
95#define CONFIG_SYS_I2C_8574_ADDR1 0x20
96#define CONFIG_SYS_I2C_8574_ADDR2 0x21
97#define CONFIG_SYS_I2C_8574A_ADDR1 0x38
98#define CONFIG_SYS_I2C_8574A_ADDR2 0x39
99#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
100#define CONFIG_SYS_I2C_RTC_ADDR 0x68
101#define SPD_EEPROM_ADDRESS 0x51
102
103
104#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
105 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
106 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
107 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
108
109
110#define I2C_8574_REVISION 0x03
111#define I2C_8574_CF 0x08
112#define I2C_8574_MPCICLKRN 0x10
113#define I2C_8574_PCI66 0x20
114#define I2C_8574_FLASHSIDE 0x40
115
116#endif
117
118
119#ifdef CONFIG_COMPACT_FLASH
120
121#define CONFIG_SYS_IDE_MAXBUS 1
122#define CONFIG_SYS_IDE_MAXDEVICE 1
123
124#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
125#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
126#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
127#define CONFIG_SYS_ATA_REG_OFFSET 0
128#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
129#define CONFIG_SYS_ATA_STRIDE 2
130
131
132#define ATA_RESET_TIME 1
133
134#endif
135
136
137
138
139#ifdef CONFIG_SATA_SIL3114
140
141#define CONFIG_SYS_SATA_MAX_DEVICE 4
142#define CONFIG_LIBATA
143#define CONFIG_LBA48
144
145#endif
146
147#ifdef CONFIG_SYS_USB_HOST
148
149
150
151#define CONFIG_USB_EHCI_FSL
152
153
154
155#if 1
156#define CONFIG_HAS_FSL_MPH_USB
157#else
158#define CONFIG_HAS_FSL_DR_USB
159#endif
160
161#endif
162
163
164
165
166#define CONFIG_SYS_DDR_BASE 0x00000000
167#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
168#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
169#define CONFIG_SYS_83XX_DDR_USES_CS0
170#define CONFIG_SYS_MEMTEST_START 0x1000
171#define CONFIG_SYS_MEMTEST_END 0x2000
172
173#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
174 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
175
176#define CONFIG_VERY_BIG_RAM
177#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
178
179#ifdef CONFIG_SYS_I2C
180#define CONFIG_SPD_EEPROM
181#endif
182
183
184#ifndef CONFIG_SPD_EEPROM
185 #define CONFIG_SYS_DDR_SIZE 256
186 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
187 | CSCONFIG_ROW_BIT_13 \
188 | CSCONFIG_COL_BIT_10)
189
190 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
191 #define CONFIG_SYS_DDR_TIMING_2 0x00000800
192#endif
193
194
195
196
197
198#define CONFIG_SYS_FLASH_CFI
199#define CONFIG_FLASH_CFI_DRIVER
200#define CONFIG_SYS_FLASH_BASE 0xFE000000
201#define CONFIG_SYS_FLASH_EMPTY_INFO
202
203#define CONFIG_SYS_MAX_FLASH_SECT 135
204#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
205#define CONFIG_SYS_FLASH_WRITE_TOUT 500
206#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
207
208
209
210#define CONFIG_SYS_FLASH_QUIET_TEST
211#define CONFIG_SYS_MAX_FLASH_BANKS 2
212#define CONFIG_SYS_FLASH_BANKS_LIST \
213 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
214#define CONFIG_SYS_FLASH_SIZE 16
215#define CONFIG_SYS_FLASH_PROTECTION 1
216
217
218
219#ifdef CONFIG_VSC7385_ENET
220
221#define CONFIG_TSEC2
222
223
224#define CONFIG_VSC7385_IMAGE 0xFEFFE000
225#define CONFIG_VSC7385_IMAGE_SIZE 8192
226
227#endif
228
229
230
231
232
233
234
235#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
236 | BR_PS_16 \
237 | BR_MS_GPCM \
238 | BR_V)
239#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
240 | OR_UPM_XAM \
241 | OR_GPCM_CSNT \
242 | OR_GPCM_ACS_DIV2 \
243 | OR_GPCM_XACS \
244 | OR_GPCM_SCY_15 \
245 | OR_GPCM_TRLX_SET \
246 | OR_GPCM_EHTR_SET \
247 | OR_GPCM_EAD)
248#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
249#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
250
251
252
253#define CONFIG_SYS_VSC7385_BASE 0xF8000000
254
255#ifdef CONFIG_VSC7385_ENET
256
257#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
258 | BR_PS_8 \
259 | BR_MS_GPCM \
260 | BR_V)
261#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
262 | OR_GPCM_CSNT \
263 | OR_GPCM_XACS \
264 | OR_GPCM_SCY_15 \
265 | OR_GPCM_SETA \
266 | OR_GPCM_TRLX_SET \
267 | OR_GPCM_EHTR_SET \
268 | OR_GPCM_EAD)
269
270#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
271#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
272
273#endif
274
275
276
277#define CONFIG_SYS_LED_BASE 0xF9000000
278#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
279 | BR_PS_8 \
280 | BR_MS_GPCM \
281 | BR_V)
282#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
283 | OR_GPCM_CSNT \
284 | OR_GPCM_ACS_DIV2 \
285 | OR_GPCM_XACS \
286 | OR_GPCM_SCY_9 \
287 | OR_GPCM_TRLX_SET \
288 | OR_GPCM_EHTR_SET \
289 | OR_GPCM_EAD)
290
291
292
293#ifdef CONFIG_COMPACT_FLASH
294
295#define CONFIG_SYS_CF_BASE 0xF0000000
296
297#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
298 | BR_PS_16 \
299 | BR_MS_UPMA \
300 | BR_V)
301#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
302
303#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
304#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
305
306#endif
307
308
309
310
311#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
312
313#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
314#define CONFIG_SYS_RAMBOOT
315#else
316#undef CONFIG_SYS_RAMBOOT
317#endif
318
319#define CONFIG_SYS_INIT_RAM_LOCK
320#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
321#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
322
323#define CONFIG_SYS_GBL_DATA_OFFSET \
324 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
325#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
326
327
328#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
329#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
330
331
332
333
334
335
336
337#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
338#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
339#define CONFIG_SYS_LBC_LBCR 0x00000000
340
341
342#define CONFIG_SYS_LBC_LSRT 0x32000000
343
344#define CONFIG_SYS_LBC_MRTPR 0x20000000
345
346
347
348
349#define CONFIG_CONS_INDEX 1
350#define CONFIG_SYS_NS16550_SERIAL
351#define CONFIG_SYS_NS16550_REG_SIZE 1
352#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
353
354#define CONFIG_SYS_BAUDRATE_TABLE \
355 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
356
357#define CONSOLE ttyS0
358
359#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
360#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
361
362
363
364
365#ifdef CONFIG_PCI
366#define CONFIG_PCI_INDIRECT_BRIDGE
367
368#define CONFIG_MPC83XX_PCI2
369
370
371
372
373
374#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
375#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
376#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
377#define CONFIG_SYS_PCI1_MMIO_BASE \
378 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
379#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
380#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
381#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
382#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
383#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
384
385#ifdef CONFIG_MPC83XX_PCI2
386#define CONFIG_SYS_PCI2_MEM_BASE \
387 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
388#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
389#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
390#define CONFIG_SYS_PCI2_MMIO_BASE \
391 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
392#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
393#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
394#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
395#define CONFIG_SYS_PCI2_IO_PHYS \
396 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
397#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000
398#endif
399
400#ifndef CONFIG_PCI_PNP
401 #define PCI_ENET0_IOADDR 0x00000000
402 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
403 #define PCI_IDSEL_NUMBER 0x0f
404#endif
405
406#define CONFIG_PCI_SCAN_SHOW
407
408#endif
409
410#define CONFIG_PCI_66M
411#ifdef CONFIG_PCI_66M
412#define CONFIG_83XX_CLKIN 66666666
413#else
414#define CONFIG_83XX_CLKIN 33333333
415#endif
416
417
418
419#ifdef CONFIG_TSEC_ENET
420
421#define CONFIG_MII
422
423#define CONFIG_TSEC1
424
425#ifdef CONFIG_TSEC1
426#define CONFIG_HAS_ETH0
427#define CONFIG_TSEC1_NAME "TSEC0"
428#define CONFIG_SYS_TSEC1_OFFSET 0x24000
429#define TSEC1_PHY_ADDR 0x1c
430#define TSEC1_PHYIDX 0
431#define TSEC1_FLAGS TSEC_GIGABIT
432#endif
433
434#ifdef CONFIG_TSEC2
435#define CONFIG_HAS_ETH1
436#define CONFIG_TSEC2_NAME "TSEC1"
437#define CONFIG_SYS_TSEC2_OFFSET 0x25000
438
439#define TSEC2_PHY_ADDR 4
440#define TSEC2_PHYIDX 0
441#define TSEC2_FLAGS TSEC_GIGABIT
442#endif
443
444#define CONFIG_ETHPRIME "Freescale TSEC"
445
446#endif
447
448
449
450
451#define CONFIG_ENV_OVERWRITE
452
453#ifndef CONFIG_SYS_RAMBOOT
454 #define CONFIG_ENV_ADDR \
455 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
456 #define CONFIG_ENV_SECT_SIZE 0x10000
457 #define CONFIG_ENV_SIZE 0x2000
458#else
459 #undef CONFIG_FLASH_CFI_DRIVER
460 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
461 #define CONFIG_ENV_SIZE 0x2000
462#endif
463
464#define CONFIG_LOADS_ECHO
465#define CONFIG_SYS_LOADS_BAUD_CHANGE
466
467
468
469
470#define CONFIG_BOOTP_BOOTFILESIZE
471#define CONFIG_BOOTP_BOOTPATH
472#define CONFIG_BOOTP_GATEWAY
473#define CONFIG_BOOTP_HOSTNAME
474
475#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
476 || defined(CONFIG_USB_STORAGE)
477 #define CONFIG_SUPPORT_VFAT
478#endif
479
480#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
481#endif
482
483
484#undef CONFIG_WATCHDOG
485
486
487
488
489#define CONFIG_SYS_LONGHELP
490#define CONFIG_CMDLINE_EDITING
491#define CONFIG_AUTO_COMPLETE
492
493#define CONFIG_SYS_LOAD_ADDR 0x2000000
494#define CONFIG_LOADADDR 800000
495
496
497
498
499
500
501
502#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
503#define CONFIG_SYS_BOOTM_LEN (64 << 20)
504
505#define CONFIG_SYS_HRCW_LOW (\
506 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
507 HRCWL_DDR_TO_SCB_CLK_1X1 |\
508 HRCWL_CSB_TO_CLKIN_4X1 |\
509 HRCWL_VCO_1X2 |\
510 HRCWL_CORE_TO_CSB_2X1)
511
512#ifdef CONFIG_SYS_LOWBOOT
513#define CONFIG_SYS_HRCW_HIGH (\
514 HRCWH_PCI_HOST |\
515 HRCWH_32_BIT_PCI |\
516 HRCWH_PCI1_ARBITER_ENABLE |\
517 HRCWH_PCI2_ARBITER_ENABLE |\
518 HRCWH_CORE_ENABLE |\
519 HRCWH_FROM_0X00000100 |\
520 HRCWH_BOOTSEQ_DISABLE |\
521 HRCWH_SW_WATCHDOG_DISABLE |\
522 HRCWH_ROM_LOC_LOCAL_16BIT |\
523 HRCWH_TSEC1M_IN_GMII |\
524 HRCWH_TSEC2M_IN_GMII)
525#else
526#define CONFIG_SYS_HRCW_HIGH (\
527 HRCWH_PCI_HOST |\
528 HRCWH_32_BIT_PCI |\
529 HRCWH_PCI1_ARBITER_ENABLE |\
530 HRCWH_PCI2_ARBITER_ENABLE |\
531 HRCWH_CORE_ENABLE |\
532 HRCWH_FROM_0XFFF00100 |\
533 HRCWH_BOOTSEQ_DISABLE |\
534 HRCWH_SW_WATCHDOG_DISABLE |\
535 HRCWH_ROM_LOC_LOCAL_16BIT |\
536 HRCWH_TSEC1M_IN_GMII |\
537 HRCWH_TSEC2M_IN_GMII)
538#endif
539
540
541
542
543#define CONFIG_SYS_ACR_PIPE_DEP 3
544#define CONFIG_SYS_ACR_RPTCNT 3
545#define CONFIG_SYS_SPCR_TSEC1EP 3
546#define CONFIG_SYS_SPCR_TSEC2EP 3
547#define CONFIG_SYS_SCCR_TSEC1CM 1
548#define CONFIG_SYS_SCCR_TSEC2CM 1
549#define CONFIG_SYS_SCCR_USBMPHCM 3
550#define CONFIG_SYS_SCCR_USBDRCM 0
551
552
553
554
555
556#define CONFIG_SYS_SICRH SICRH_TSOBI1
557
558#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
559
560#define CONFIG_SYS_HID0_INIT 0x00000000
561#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
562
563#define CONFIG_SYS_HID2 HID2_HBE
564#define CONFIG_HIGH_BATS 1
565
566
567#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
568 | BATL_PP_RW \
569 | BATL_MEMCOHERENCE)
570#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
571 | BATU_BL_256M \
572 | BATU_VS \
573 | BATU_VP)
574
575
576#ifdef CONFIG_PCI
577#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
578 | BATL_PP_RW \
579 | BATL_MEMCOHERENCE)
580#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
581 | BATU_BL_256M \
582 | BATU_VS \
583 | BATU_VP)
584#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
585 | BATL_PP_RW \
586 | BATL_CACHEINHIBIT \
587 | BATL_GUARDEDSTORAGE)
588#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
589 | BATU_BL_256M \
590 | BATU_VS \
591 | BATU_VP)
592#else
593#define CONFIG_SYS_IBAT1L 0
594#define CONFIG_SYS_IBAT1U 0
595#define CONFIG_SYS_IBAT2L 0
596#define CONFIG_SYS_IBAT2U 0
597#endif
598
599#ifdef CONFIG_MPC83XX_PCI2
600#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
601 | BATL_PP_RW \
602 | BATL_MEMCOHERENCE)
603#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
604 | BATU_BL_256M \
605 | BATU_VS \
606 | BATU_VP)
607#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
608 | BATL_PP_RW \
609 | BATL_CACHEINHIBIT \
610 | BATL_GUARDEDSTORAGE)
611#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
612 | BATU_BL_256M \
613 | BATU_VS \
614 | BATU_VP)
615#else
616#define CONFIG_SYS_IBAT3L 0
617#define CONFIG_SYS_IBAT3U 0
618#define CONFIG_SYS_IBAT4L 0
619#define CONFIG_SYS_IBAT4U 0
620#endif
621
622
623#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
624 | BATL_PP_RW \
625 | BATL_CACHEINHIBIT \
626 | BATL_GUARDEDSTORAGE)
627#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
628 | BATU_BL_256M \
629 | BATU_VS \
630 | BATU_VP)
631
632
633#define CONFIG_SYS_IBAT6L (0xF0000000 \
634 | BATL_PP_RW \
635 | BATL_MEMCOHERENCE \
636 | BATL_GUARDEDSTORAGE)
637#define CONFIG_SYS_IBAT6U (0xF0000000 \
638 | BATU_BL_256M \
639 | BATU_VS \
640 | BATU_VP)
641
642#define CONFIG_SYS_IBAT7L 0
643#define CONFIG_SYS_IBAT7U 0
644
645#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
646#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
647#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
648#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
649#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
650#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
651#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
652#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
653#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
654#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
655#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
656#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
657#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
658#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
659#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
660#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
661
662#if defined(CONFIG_CMD_KGDB)
663#define CONFIG_KGDB_BAUDRATE 230400
664#endif
665
666
667
668
669#define CONFIG_ENV_OVERWRITE
670
671#define CONFIG_NETDEV "eth0"
672
673
674#define CONFIG_ROOTPATH "/nfsroot/rootfs"
675#define CONFIG_BOOTFILE "uImage"
676
677#define CONFIG_UBOOTPATH "u-boot.bin"
678
679#ifdef CONFIG_MPC8349ITX
680#define CONFIG_FDTFILE "mpc8349emitx.dtb"
681#else
682#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
683#endif
684
685
686#define CONFIG_EXTRA_ENV_SETTINGS \
687 "console=" __stringify(CONSOLE) "\0" \
688 "netdev=" CONFIG_NETDEV "\0" \
689 "uboot=" CONFIG_UBOOTPATH "\0" \
690 "tftpflash=tftpboot $loadaddr $uboot; " \
691 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
692 " +$filesize; " \
693 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
694 " +$filesize; " \
695 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
696 " $filesize; " \
697 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
698 " +$filesize; " \
699 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
700 " $filesize\0" \
701 "fdtaddr=780000\0" \
702 "fdtfile=" CONFIG_FDTFILE "\0"
703
704#define CONFIG_NFSBOOTCOMMAND \
705 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
706 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
707 " console=$console,$baudrate $othbootargs; " \
708 "tftp $loadaddr $bootfile;" \
709 "tftp $fdtaddr $fdtfile;" \
710 "bootm $loadaddr - $fdtaddr"
711
712#define CONFIG_RAMBOOTCOMMAND \
713 "setenv bootargs root=/dev/ram rw" \
714 " console=$console,$baudrate $othbootargs; " \
715 "tftp $ramdiskaddr $ramdiskfile;" \
716 "tftp $loadaddr $bootfile;" \
717 "tftp $fdtaddr $fdtfile;" \
718 "bootm $loadaddr $ramdiskaddr $fdtaddr"
719
720#endif
721