1/* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __CONFIG_H 10#define __CONFIG_H 11 12#include <asm/arch-ag101/ag101.h> 13 14/* 15 * CPU and Board Configuration Options 16 */ 17#define CONFIG_ADP_AG101P 18 19#define CONFIG_USE_INTERRUPT 20 21#define CONFIG_SKIP_LOWLEVEL_INIT 22 23#define CONFIG_CMDLINE_EDITING 24 25#define CONFIG_ARCH_MAP_SYSMEM 26 27#define CONFIG_BOOTP_SEND_HOSTNAME 28#define CONFIG_BOOTP_SERVERIP 29 30#ifndef CONFIG_SKIP_LOWLEVEL_INIT 31#define CONFIG_MEM_REMAP 32#endif 33 34#ifdef CONFIG_SKIP_LOWLEVEL_INIT 35#define CONFIG_SYS_TEXT_BASE 0x00500000 36#ifdef CONFIG_OF_CONTROL 37#undef CONFIG_OF_SEPARATE 38#define CONFIG_OF_EMBED 39#endif 40#else 41#ifdef CONFIG_MEM_REMAP 42#define CONFIG_SYS_TEXT_BASE 0x80000000 43#else 44#define CONFIG_SYS_TEXT_BASE 0x00000000 45#endif 46#endif 47 48/* 49 * Timer 50 */ 51#define CONFIG_SYS_CLK_FREQ 39062500 52#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 53 54/* 55 * Use Externel CLOCK or PCLK 56 */ 57#undef CONFIG_FTRTC010_EXTCLK 58 59#ifndef CONFIG_FTRTC010_EXTCLK 60#define CONFIG_FTRTC010_PCLK 61#endif 62 63#ifdef CONFIG_FTRTC010_EXTCLK 64#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 65#else 66#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 67#endif 68 69#define TIMER_LOAD_VAL 0xffffffff 70 71/* 72 * Real Time Clock 73 */ 74#define CONFIG_RTC_FTRTC010 75 76/* 77 * Real Time Clock Divider 78 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 79 */ 80#define OSC_5MHZ (5*1000000) 81#define OSC_CLK (4*OSC_5MHZ) 82#define RTC_DIV_COUNT (0.5) /* Why?? */ 83 84/* 85 * Serial console configuration 86 */ 87 88/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 89#define CONFIG_CONS_INDEX 1 90#define CONFIG_SYS_NS16550_SERIAL 91#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 92#ifndef CONFIG_DM_SERIAL 93#define CONFIG_SYS_NS16550_REG_SIZE -4 94#endif 95#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 96 97/* 98 * SD (MMC) controller 99 */ 100#define CONFIG_FTSDC010 101#define CONFIG_FTSDC010_NUMBER 1 102#define CONFIG_FTSDC010_SDIO 103 104/* 105 * Miscellaneous configurable options 106 */ 107#define CONFIG_SYS_LONGHELP /* undef to save memory */ 108 109/* 110 * Size of malloc() pool 111 */ 112/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 113#define CONFIG_SYS_MALLOC_LEN (512 << 10) 114 115/* 116 * AHB Controller configuration 117 */ 118#define CONFIG_FTAHBC020S 119 120#ifdef CONFIG_FTAHBC020S 121#include <faraday/ftahbc020s.h> 122 123/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 124#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 125 126/* 127 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 128 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 129 * in C language. 130 */ 131#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 132 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 133 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 134#endif 135 136/* 137 * Watchdog 138 */ 139#define CONFIG_FTWDT010_WATCHDOG 140 141/* 142 * PMU Power controller configuration 143 */ 144#define CONFIG_PMU 145#define CONFIG_FTPMU010_POWER 146 147#ifdef CONFIG_FTPMU010_POWER 148#include <faraday/ftpmu010.h> 149#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 150#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 151 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 152 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 153 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 154 FTPMU010_SDRAMHTC_CKE_DCSR | \ 155 FTPMU010_SDRAMHTC_DQM_DCSR | \ 156 FTPMU010_SDRAMHTC_SDCLK_DCSR) 157#endif 158 159/* 160 * SDRAM controller configuration 161 */ 162#define CONFIG_FTSDMC021 163 164#ifdef CONFIG_FTSDMC021 165#include <faraday/ftsdmc021.h> 166 167#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 168 FTSDMC021_TP1_TRP(1) | \ 169 FTSDMC021_TP1_TRCD(1) | \ 170 FTSDMC021_TP1_TRF(3) | \ 171 FTSDMC021_TP1_TWR(1) | \ 172 FTSDMC021_TP1_TCL(2)) 173 174#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 175 FTSDMC021_TP2_INI_REFT(8) | \ 176 FTSDMC021_TP2_REF_INTV(0x180)) 177 178/* 179 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 180 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 181 * C language. 182 */ 183#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 184 FTSDMC021_CR1_DSZ(3) | \ 185 FTSDMC021_CR1_MBW(2) | \ 186 FTSDMC021_CR1_BNKSIZE(6)) 187 188#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 189 FTSDMC021_CR2_IREF | \ 190 FTSDMC021_CR2_ISMR) 191 192#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 193#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 194 CONFIG_SYS_FTSDMC021_BANK0_BASE) 195 196#define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 197 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 198#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 199 CONFIG_SYS_FTSDMC021_BANK1_BASE) 200#endif 201 202/* 203 * Physical Memory Map 204 */ 205#ifdef CONFIG_SKIP_LOWLEVEL_INIT 206#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 207#else 208#ifdef CONFIG_MEM_REMAP 209#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 210#else 211#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 212#endif 213#endif 214 215#define PHYS_SDRAM_1 \ 216 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 217 218#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 219 220#ifdef CONFIG_SKIP_LOWLEVEL_INIT 221#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 222#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 223#else 224#ifdef CONFIG_MEM_REMAP 225#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 226#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 227#else 228#define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 229#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 230#endif 231#endif 232 233#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 234 235#ifdef CONFIG_MEM_REMAP 236#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 237 GENERATED_GBL_DATA_SIZE) 238#else 239#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 240 GENERATED_GBL_DATA_SIZE) 241#endif /* CONFIG_MEM_REMAP */ 242 243/* 244 * Load address and memory test area should agree with 245 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 246 */ 247#define CONFIG_SYS_LOAD_ADDR 0x300000 248 249/* memtest works on 63 MB in DRAM */ 250#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 251#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 252 253/* 254 * Static memory controller configuration 255 */ 256#define CONFIG_FTSMC020 257 258#ifdef CONFIG_FTSMC020 259#include <faraday/ftsmc020.h> 260 261#define CONFIG_SYS_FTSMC020_CONFIGS { \ 262 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 263 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 264} 265 266#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 267#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 268 FTSMC020_BANK_SIZE_32M | \ 269 FTSMC020_BANK_MBW_32) 270 271#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 272 FTSMC020_TPR_AST(1) | \ 273 FTSMC020_TPR_CTW(1) | \ 274 FTSMC020_TPR_ATI(1) | \ 275 FTSMC020_TPR_AT2(1) | \ 276 FTSMC020_TPR_WTC(1) | \ 277 FTSMC020_TPR_AHT(1) | \ 278 FTSMC020_TPR_TRNA(1)) 279#endif 280 281/* 282 * FLASH on ADP_AG101P is connected to BANK0 283 * Just disalbe the other BANK to avoid detection error. 284 */ 285#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 286 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 287 FTSMC020_BANK_SIZE_32M | \ 288 FTSMC020_BANK_MBW_32) 289 290#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 291 FTSMC020_TPR_CTW(3) | \ 292 FTSMC020_TPR_ATI(0xf) | \ 293 FTSMC020_TPR_AT2(3) | \ 294 FTSMC020_TPR_WTC(3) | \ 295 FTSMC020_TPR_AHT(3) | \ 296 FTSMC020_TPR_TRNA(0xf)) 297 298#define FTSMC020_BANK1_CONFIG (0x00) 299#define FTSMC020_BANK1_TIMING (0x00) 300#endif /* CONFIG_FTSMC020 */ 301 302/* 303 * FLASH and environment organization 304 */ 305/* use CFI framework */ 306#define CONFIG_SYS_FLASH_CFI 307#define CONFIG_FLASH_CFI_DRIVER 308 309#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 310#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 311#define CONFIG_SYS_CFI_FLASH_STATUS_POLL 312 313/* support JEDEC */ 314 315/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 316#ifdef CONFIG_SKIP_LOWLEVEL_INIT 317#define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 318#else 319#ifdef CONFIG_MEM_REMAP 320#define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 321#else 322#define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 323#endif 324#endif /* CONFIG_MEM_REMAP */ 325 326#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 327#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 328#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 329 330#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 331#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 332 333/* max number of memory banks */ 334/* 335 * There are 4 banks supported for this Controller, 336 * but we have only 1 bank connected to flash on board 337 */ 338#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 339#define CONFIG_SYS_MAX_FLASH_BANKS 1 340#endif 341#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 342 343/* max number of sectors on one chip */ 344#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 345#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 346#define CONFIG_SYS_MAX_FLASH_SECT 512 347 348/* environments */ 349#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 350#define CONFIG_ENV_SIZE 8192 351#define CONFIG_ENV_OVERWRITE 352 353/* 354 * For booting Linux, the board info and command line data 355 * have to be in the first 16 MB of memory, since this is 356 * the maximum mapped by the Linux kernel during initialization. 357 */ 358 359/* Initial Memory map for Linux*/ 360#define CONFIG_SYS_BOOTMAPSZ (64 << 20) 361/* Increase max gunzip size */ 362#define CONFIG_SYS_BOOTM_LEN (64 << 20) 363 364#endif /* __CONFIG_H */ 365