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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include "../board/freescale/common/ics307_clk.h"
14
15#ifdef CONFIG_RAMBOOT_PBL
16#ifdef CONFIG_SECURE_BOOT
17#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19#ifdef CONFIG_NAND
20#define CONFIG_RAMBOOT_NAND
21#endif
22#define CONFIG_BOOTSCRIPT_COPY_RAM
23#else
24#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
25#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
26#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
27#if defined(CONFIG_TARGET_P3041DS)
28#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
29#elif defined(CONFIG_TARGET_P4080DS)
30#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
31#elif defined(CONFIG_TARGET_P5020DS)
32#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
33#elif defined(CONFIG_TARGET_P5040DS)
34#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
35#endif
36#endif
37#endif
38
39#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
40
41#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
42#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
44#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
45#endif
46
47
48#define CONFIG_SYS_BOOK3E_HV
49#define CONFIG_MP
50
51#ifndef CONFIG_SYS_TEXT_BASE
52#define CONFIG_SYS_TEXT_BASE 0xeff40000
53#endif
54
55#ifndef CONFIG_RESET_VECTOR_ADDRESS
56#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
57#endif
58
59#define CONFIG_SYS_FSL_CPC
60#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
61#define CONFIG_PCIE1
62#define CONFIG_PCIE2
63#define CONFIG_FSL_PCI_INIT
64#define CONFIG_SYS_PCI_64BIT
65
66#define CONFIG_ENV_OVERWRITE
67
68#ifndef CONFIG_MTD_NOR_FLASH
69#else
70#define CONFIG_FLASH_CFI_DRIVER
71#define CONFIG_SYS_FLASH_CFI
72#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
73#endif
74
75#if defined(CONFIG_SPIFLASH)
76#define CONFIG_SYS_EXTRA_ENV_RELOC
77#define CONFIG_ENV_SPI_BUS 0
78#define CONFIG_ENV_SPI_CS 0
79#define CONFIG_ENV_SPI_MAX_HZ 10000000
80#define CONFIG_ENV_SPI_MODE 0
81#define CONFIG_ENV_SIZE 0x2000
82#define CONFIG_ENV_OFFSET 0x100000
83#define CONFIG_ENV_SECT_SIZE 0x10000
84#elif defined(CONFIG_SDCARD)
85#define CONFIG_SYS_EXTRA_ENV_RELOC
86#define CONFIG_FSL_FIXED_MMC_LOCATION
87#define CONFIG_SYS_MMC_ENV_DEV 0
88#define CONFIG_ENV_SIZE 0x2000
89#define CONFIG_ENV_OFFSET (512 * 1658)
90#elif defined(CONFIG_NAND)
91#define CONFIG_SYS_EXTRA_ENV_RELOC
92#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
93#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
94#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
95#define CONFIG_ENV_ADDR 0xffe20000
96#define CONFIG_ENV_SIZE 0x2000
97#elif defined(CONFIG_ENV_IS_NOWHERE)
98#define CONFIG_ENV_SIZE 0x2000
99#else
100#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
101#define CONFIG_ENV_SIZE 0x2000
102#define CONFIG_ENV_SECT_SIZE 0x20000
103#endif
104
105#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
106
107
108
109
110#define CONFIG_SYS_CACHE_STASHING
111#define CONFIG_BACKSIDE_L2_CACHE
112#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
113#define CONFIG_BTB
114#define CONFIG_DDR_ECC
115#ifdef CONFIG_DDR_ECC
116#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
117#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
118#endif
119
120#define CONFIG_ENABLE_36BIT_PHYS
121
122#ifdef CONFIG_PHYS_64BIT
123#define CONFIG_ADDR_MAP
124#define CONFIG_SYS_NUM_ADDR_MAP 64
125#endif
126
127#define CONFIG_POST CONFIG_SYS_POST_MEMORY
128#define CONFIG_SYS_MEMTEST_START 0x00200000
129#define CONFIG_SYS_MEMTEST_END 0x00400000
130#define CONFIG_SYS_ALT_MEMTEST
131#define CONFIG_PANIC_HANG
132
133
134
135
136#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
137#ifdef CONFIG_PHYS_64BIT
138#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
139#else
140#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
141#endif
142#define CONFIG_SYS_L3_SIZE (1024 << 10)
143#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
144
145#ifdef CONFIG_PHYS_64BIT
146#define CONFIG_SYS_DCSRBAR 0xf0000000
147#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
148#endif
149
150
151#define CONFIG_ID_EEPROM
152#define CONFIG_SYS_I2C_EEPROM_NXID
153#define CONFIG_SYS_EEPROM_BUS_NUM 0
154#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
155#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
156
157
158
159
160#define CONFIG_VERY_BIG_RAM
161#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
162#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
163
164#define CONFIG_DIMM_SLOTS_PER_CTLR 1
165#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
166
167#define CONFIG_DDR_SPD
168
169#define CONFIG_SYS_SPD_BUS_NUM 1
170#define SPD_EEPROM_ADDRESS1 0x51
171#define SPD_EEPROM_ADDRESS2 0x52
172#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
173#define CONFIG_SYS_SDRAM_SIZE 4096
174
175
176
177
178
179
180#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
181
182#define CONFIG_SYS_FLASH_BASE 0xe0000000
183#ifdef CONFIG_PHYS_64BIT
184#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
185#else
186#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
187#endif
188
189#define CONFIG_SYS_FLASH_BR_PRELIM \
190 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
191 | BR_PS_16 | BR_V)
192#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
193 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
194
195#define CONFIG_SYS_BR1_PRELIM \
196 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
197#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
198
199#define PIXIS_BASE 0xffdf0000
200#ifdef CONFIG_PHYS_64BIT
201#define PIXIS_BASE_PHYS 0xfffdf0000ull
202#else
203#define PIXIS_BASE_PHYS PIXIS_BASE
204#endif
205
206#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
207#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
208
209#define PIXIS_LBMAP_SWITCH 7
210#define PIXIS_LBMAP_MASK 0xf0
211#define PIXIS_LBMAP_SHIFT 4
212#define PIXIS_LBMAP_ALTBANK 0x40
213
214#define CONFIG_SYS_FLASH_QUIET_TEST
215#define CONFIG_FLASH_SHOW_PROGRESS 45
216
217#define CONFIG_SYS_MAX_FLASH_BANKS 2
218#define CONFIG_SYS_MAX_FLASH_SECT 1024
219#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
220#define CONFIG_SYS_FLASH_WRITE_TOUT 500
221
222#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
223
224#if defined(CONFIG_RAMBOOT_PBL)
225#define CONFIG_SYS_RAMBOOT
226#endif
227
228
229#ifdef CONFIG_NAND_FSL_ELBC
230#define CONFIG_SYS_NAND_BASE 0xffa00000
231#ifdef CONFIG_PHYS_64BIT
232#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
233#else
234#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
235#endif
236
237#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
238#define CONFIG_SYS_MAX_NAND_DEVICE 1
239#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
240
241
242#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
243 | (2<<BR_DECC_SHIFT) \
244 | BR_PS_8 \
245 | BR_MS_FCM \
246 | BR_V)
247#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
248 | OR_FCM_PGS \
249 | OR_FCM_CSCT \
250 | OR_FCM_CST \
251 | OR_FCM_CHT \
252 | OR_FCM_SCY_1 \
253 | OR_FCM_TRLX \
254 | OR_FCM_EHTR)
255
256#ifdef CONFIG_NAND
257#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
258#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
259#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM
260#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM
261#else
262#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM
263#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM
264#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM
265#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM
266#endif
267#else
268#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM
269#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM
270#endif
271
272#define CONFIG_SYS_FLASH_EMPTY_INFO
273#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
274#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
275
276#define CONFIG_BOARD_EARLY_INIT_R
277#define CONFIG_MISC_INIT_R
278
279#define CONFIG_HWCONFIG
280
281
282#define CONFIG_L1_INIT_RAM
283#define CONFIG_SYS_INIT_RAM_LOCK
284#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
285#ifdef CONFIG_PHYS_64BIT
286#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
287#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
288
289#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
290 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
291 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
292#else
293#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
294#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
295#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
296#endif
297#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
298
299#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
300#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
301
302#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
303#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
304
305
306
307
308
309#define CONFIG_CONS_INDEX 1
310#define CONFIG_SYS_NS16550_SERIAL
311#define CONFIG_SYS_NS16550_REG_SIZE 1
312#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
313
314#define CONFIG_SYS_BAUDRATE_TABLE \
315 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
316
317#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
318#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
319#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
320#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
321
322
323#define CONFIG_SYS_I2C
324#define CONFIG_SYS_I2C_FSL
325#define CONFIG_SYS_FSL_I2C_SPEED 400000
326#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
327#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
328#define CONFIG_SYS_FSL_I2C2_SPEED 400000
329#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
330#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
331
332
333
334
335#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
336#ifdef CONFIG_PHYS_64BIT
337#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
338#else
339#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
340#endif
341#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000
342
343#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
344#ifdef CONFIG_PHYS_64BIT
345#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
346#else
347#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
348#endif
349#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000
350
351
352
353
354
355#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
356#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
357#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
358#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
359
360
361
362
363#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
364#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
365#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
366
367
368#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
369#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
370
371
372
373
374#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
375#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
376#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
377 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
378#endif
379
380
381
382
383#define CONFIG_SF_DEFAULT_SPEED 10000000
384#define CONFIG_SF_DEFAULT_MODE 0
385
386
387
388
389
390
391
392#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
393#ifdef CONFIG_PHYS_64BIT
394#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
395#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
396#else
397#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
398#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
399#endif
400#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
401#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
402#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
403#ifdef CONFIG_PHYS_64BIT
404#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
405#else
406#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
407#endif
408#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
409
410
411#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
412#ifdef CONFIG_PHYS_64BIT
413#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
414#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
415#else
416#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
417#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
418#endif
419#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
420#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
421#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
422#ifdef CONFIG_PHYS_64BIT
423#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
424#else
425#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
426#endif
427#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
428
429
430#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
431#ifdef CONFIG_PHYS_64BIT
432#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
433#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
434#else
435#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
436#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
437#endif
438#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
439#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
440#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
441#ifdef CONFIG_PHYS_64BIT
442#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
443#else
444#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
445#endif
446#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
447
448
449#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
450#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
451#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000
452#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
453#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
454#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
455
456
457#define CONFIG_SYS_DPAA_QBMAN
458#define CONFIG_SYS_BMAN_NUM_PORTALS 10
459#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
460#ifdef CONFIG_PHYS_64BIT
461#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
462#else
463#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
464#endif
465#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
466#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
467#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
468#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
469#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
470#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
471 CONFIG_SYS_BMAN_CENA_SIZE)
472#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
473#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
474#define CONFIG_SYS_QMAN_NUM_PORTALS 10
475#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
476#ifdef CONFIG_PHYS_64BIT
477#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
478#else
479#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
480#endif
481#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
482#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
483#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
484#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
485#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
486#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
487 CONFIG_SYS_QMAN_CENA_SIZE)
488#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
489#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
490
491#define CONFIG_SYS_DPAA_FMAN
492#define CONFIG_SYS_DPAA_PME
493
494#if defined(CONFIG_SPIFLASH)
495
496
497
498
499#define CONFIG_SYS_QE_FW_IN_SPIFLASH
500#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
501#elif defined(CONFIG_SDCARD)
502
503
504
505
506
507#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
508#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
509#elif defined(CONFIG_NAND)
510#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
511#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
512#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
513
514
515
516
517
518
519
520#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
521#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
522#else
523#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
524#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
525#endif
526#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
527#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
528
529#ifdef CONFIG_SYS_DPAA_FMAN
530#define CONFIG_FMAN_ENET
531#define CONFIG_PHYLIB_10G
532#define CONFIG_PHY_VITESSE
533#define CONFIG_PHY_TERANETICS
534#endif
535
536#ifdef CONFIG_PCI
537#define CONFIG_PCI_INDIRECT_BRIDGE
538
539#define CONFIG_PCI_SCAN_SHOW
540#endif
541
542
543#ifdef CONFIG_FSL_SATA_V2
544#define CONFIG_LIBATA
545#define CONFIG_FSL_SATA
546
547#define CONFIG_SYS_SATA_MAX_DEVICE 2
548#define CONFIG_SATA1
549#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
550#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
551#define CONFIG_SATA2
552#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
553#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
554
555#define CONFIG_LBA48
556#endif
557
558#ifdef CONFIG_FMAN_ENET
559#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
560#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
561#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
562#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
563#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
564
565#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
566#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
567#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
568#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
569#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
570
571#define CONFIG_SYS_TBIPA_VALUE 8
572#define CONFIG_MII
573#define CONFIG_ETHPRIME "FM1@DTSEC1"
574#endif
575
576
577
578
579#define CONFIG_LOADS_ECHO
580#define CONFIG_SYS_LOADS_BAUD_CHANGE
581
582
583
584
585#define CONFIG_HAS_FSL_DR_USB
586#define CONFIG_HAS_FSL_MPH_USB
587
588#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
589#define CONFIG_USB_EHCI_FSL
590#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
591#endif
592
593#ifdef CONFIG_MMC
594#define CONFIG_FSL_ESDHC
595#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
596#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
597#endif
598
599
600
601
602#define CONFIG_SYS_LONGHELP
603#define CONFIG_CMDLINE_EDITING
604#define CONFIG_AUTO_COMPLETE
605#define CONFIG_SYS_LOAD_ADDR 0x2000000
606
607
608
609
610
611
612#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
613#define CONFIG_SYS_BOOTM_LEN (64 << 20)
614
615#ifdef CONFIG_CMD_KGDB
616#define CONFIG_KGDB_BAUDRATE 230400
617#endif
618
619
620
621
622#define CONFIG_ROOTPATH "/opt/nfsroot"
623#define CONFIG_BOOTFILE "uImage"
624#define CONFIG_UBOOTPATH u-boot.bin
625
626
627#define CONFIG_LOADADDR 1000000
628
629#ifdef CONFIG_TARGET_P4080DS
630#define __USB_PHY_TYPE ulpi
631#else
632#define __USB_PHY_TYPE utmi
633#endif
634
635#define CONFIG_EXTRA_ENV_SETTINGS \
636 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
637 "bank_intlv=cs0_cs1;" \
638 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
639 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
640 "netdev=eth0\0" \
641 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
642 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
643 "tftpflash=tftpboot $loadaddr $uboot && " \
644 "protect off $ubootaddr +$filesize && " \
645 "erase $ubootaddr +$filesize && " \
646 "cp.b $loadaddr $ubootaddr $filesize && " \
647 "protect on $ubootaddr +$filesize && " \
648 "cmp.b $loadaddr $ubootaddr $filesize\0" \
649 "consoledev=ttyS0\0" \
650 "ramdiskaddr=2000000\0" \
651 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
652 "fdtaddr=1e00000\0" \
653 "fdtfile=p4080ds/p4080ds.dtb\0" \
654 "bdev=sda3\0"
655
656#define CONFIG_HDBOOT \
657 "setenv bootargs root=/dev/$bdev rw " \
658 "console=$consoledev,$baudrate $othbootargs;" \
659 "tftp $loadaddr $bootfile;" \
660 "tftp $fdtaddr $fdtfile;" \
661 "bootm $loadaddr - $fdtaddr"
662
663#define CONFIG_NFSBOOTCOMMAND \
664 "setenv bootargs root=/dev/nfs rw " \
665 "nfsroot=$serverip:$rootpath " \
666 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
667 "console=$consoledev,$baudrate $othbootargs;" \
668 "tftp $loadaddr $bootfile;" \
669 "tftp $fdtaddr $fdtfile;" \
670 "bootm $loadaddr - $fdtaddr"
671
672#define CONFIG_RAMBOOTCOMMAND \
673 "setenv bootargs root=/dev/ram rw " \
674 "console=$consoledev,$baudrate $othbootargs;" \
675 "tftp $ramdiskaddr $ramdiskfile;" \
676 "tftp $loadaddr $bootfile;" \
677 "tftp $fdtaddr $fdtfile;" \
678 "bootm $loadaddr $ramdiskaddr $fdtaddr"
679
680#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
681
682#include <asm/fsl_secure_boot.h>
683
684#endif
685