1/* 2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef _CONFIG_DB_MV7846MP_GP_H 8#define _CONFIG_DB_MV7846MP_GP_H 9 10/* 11 * High Level Configuration Options (easy to change) 12 */ 13#define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 14 15#define CONFIG_DISPLAY_BOARDINFO_LATE 16 17/* 18 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 19 * for DDR ECC byte filling in the SPL before loading the main 20 * U-Boot into it. 21 */ 22#define CONFIG_SYS_TEXT_BASE 0x00800000 23#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 24 25/* I2C */ 26#define CONFIG_SYS_I2C 27#define CONFIG_SYS_I2C_MVTWSI 28#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 29#define CONFIG_SYS_I2C_SLAVE 0x0 30#define CONFIG_SYS_I2C_SPEED 100000 31 32/* USB/EHCI configuration */ 33#define CONFIG_EHCI_IS_TDI 34#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 35 36/* SPI NOR flash default params, used by sf commands */ 37#define CONFIG_SF_DEFAULT_SPEED 1000000 38#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 39 40/* Environment in SPI NOR flash */ 41#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 42#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 43#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 44 45#define CONFIG_PHY_MARVELL /* there is a marvell phy */ 46#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 47 48#define CONFIG_SYS_ALT_MEMTEST 49 50/* SATA support */ 51#define CONFIG_SYS_SATA_MAX_DEVICE 2 52#define CONFIG_SATA_MV 53#define CONFIG_LIBATA 54#define CONFIG_LBA48 55 56/* Additional FS support/configuration */ 57#define CONFIG_SUPPORT_VFAT 58 59/* PCIe support */ 60#ifndef CONFIG_SPL_BUILD 61#define CONFIG_PCI_MVEBU 62#define CONFIG_PCI_SCAN_SHOW 63#endif 64 65/* NAND */ 66#define CONFIG_SYS_NAND_USE_FLASH_BBT 67#define CONFIG_SYS_NAND_ONFI_DETECTION 68 69/* 70 * mv-common.h should be defined after CMD configs since it used them 71 * to enable certain macros 72 */ 73#include "mv-common.h" 74 75/* 76 * Memory layout while starting into the bin_hdr via the 77 * BootROM: 78 * 79 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 80 * 0x4000.4030 bin_hdr start address 81 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 82 * 0x4007.fffc BootROM stack top 83 * 84 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 85 * L2 cache thus cannot be used. 86 */ 87 88/* SPL */ 89/* Defines for SPL */ 90#define CONFIG_SPL_FRAMEWORK 91#define CONFIG_SPL_TEXT_BASE 0x40004030 92#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 93 94#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 95#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 96 97#ifdef CONFIG_SPL_BUILD 98#define CONFIG_SYS_MALLOC_SIMPLE 99#endif 100 101#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 102#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 103 104/* SPL related SPI defines */ 105#define CONFIG_SPL_SPI_LOAD 106#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 107#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 108 109/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 110#define CONFIG_SPD_EEPROM 0x4e 111#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 112 113#endif /* _CONFIG_DB_MV7846MP_GP_H */ 114