LXR uboot/include/configs/km/km83xx-common.h

   1/*
   2 * (C) Copyright 2010
   3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef __CONFIG_KM83XX_H
   9#define __CONFIG_KM83XX_H
  10
  11/* include common defines/options for all Keymile boards */
  12#include "keymile-common.h"
  13#include "km-powerpc.h"
  14
  15#define CONFIG_MISC_INIT_R
  16/*
  17 * System Clock Setup
  18 */
  19#define CONFIG_83XX_CLKIN               66000000
  20#define CONFIG_SYS_CLK_FREQ             66000000
  21#define CONFIG_83XX_PCICLK              66000000
  22
  23/*
  24 * IMMR new address
  25 */
  26#define CONFIG_SYS_IMMR         0xE0000000
  27
  28/*
  29 * Bus Arbitration Configuration Register (ACR)
  30 */
  31#define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  32#define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  33#define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  34#define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  35
  36/*
  37 * DDR Setup
  38 */
  39#define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  40#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  41#define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  42
  43#define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  44#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  45                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  46
  47#define CFG_83XX_DDR_USES_CS0
  48
  49/*
  50 * Manually set up DDR parameters
  51 */
  52#define CONFIG_DDR_II
  53#define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  54
  55/*
  56 * The reserved memory
  57 */
  58#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  59#define CONFIG_SYS_FLASH_BASE           0xF0000000
  60
  61#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  62#define CONFIG_SYS_RAMBOOT
  63#endif
  64
  65/* Reserve 768 kB for Mon */
  66#define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  67
  68/*
  69 * Initial RAM Base Address Setup
  70 */
  71#define CONFIG_SYS_INIT_RAM_LOCK
  72#define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  73#define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  74#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  75                                                GENERATED_GBL_DATA_SIZE)
  76
  77/*
  78 * Init Local Bus Memory Controller:
  79 *
  80 * Bank Bus     Machine PortSz  Size  Device
  81 * ---- ---     ------- ------  -----  ------
  82 *  0   Local   GPCM    16 bit  256MB FLASH
  83 *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
  84 *
  85 */
  86/*
  87 * FLASH on the Local Bus
  88 */
  89#define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
  90#define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
  91#define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
  92#define CONFIG_SYS_FLASH_PROTECTION
  93#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  94
  95#define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
  96#define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
  97
  98#define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
  99                                BR_PS_16 | /* 16 bit port size */ \
 100                                BR_MS_GPCM | /* MSEL = GPCM */ \
 101                                BR_V)
 102
 103#define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 104                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 105                                OR_GPCM_SCY_5 | \
 106                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 107
 108#define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 109#define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 110#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 111
 112/*
 113 * PRIO1/PIGGY on the local bus CS1
 114 */
 115/* Window base at flash base */
 116#define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_KMBEC_FPGA_BASE
 117#define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 118
 119#define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 120                                BR_PS_8 | /* 8 bit port size */ \
 121                                BR_MS_GPCM | /* MSEL = GPCM */ \
 122                                BR_V)
 123#define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 124                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 125                                OR_GPCM_SCY_2 | \
 126                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 127
 128/*
 129 * Serial Port
 130 */
 131#define CONFIG_CONS_INDEX       1
 132#define CONFIG_SYS_NS16550_SERIAL
 133#define CONFIG_SYS_NS16550_REG_SIZE     1
 134#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 135
 136#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 137#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 138
 139/*
 140 * QE UEC ethernet configuration
 141 */
 142#define CONFIG_UEC_ETH
 143#define CONFIG_ETHPRIME         "UEC0"
 144
 145#if !defined(CONFIG_MPC8309)
 146#define CONFIG_UEC_ETH1         /* GETH1 */
 147#define UEC_VERBOSE_DEBUG       1
 148#endif
 149
 150#ifdef CONFIG_UEC_ETH1
 151#define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 152#define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 153#define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 154#define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 155#define CONFIG_SYS_UEC1_PHY_ADDR        0
 156#define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 157#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 158#endif
 159
 160/*
 161 * Environment
 162 */
 163
 164#ifndef CONFIG_SYS_RAMBOOT
 165#ifndef CONFIG_ENV_ADDR
 166#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 167                                        CONFIG_SYS_MONITOR_LEN)
 168#endif
 169#define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 170#ifndef CONFIG_ENV_OFFSET
 171#define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 172#endif
 173
 174/* Address and size of Redundant Environment Sector     */
 175#define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 176                                                CONFIG_ENV_SECT_SIZE)
 177#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 178
 179#else /* CFG_SYS_RAMBOOT */
 180#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 181#define CONFIG_ENV_SIZE         0x2000
 182#endif /* CFG_SYS_RAMBOOT */
 183
 184/* I2C */
 185#define CONFIG_SYS_I2C
 186#define CONFIG_SYS_NUM_I2C_BUSES        4
 187#define CONFIG_SYS_I2C_MAX_HOPS         1
 188#define CONFIG_SYS_I2C_FSL
 189#define CONFIG_SYS_FSL_I2C_SPEED        200000
 190#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 191#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 192#define CONFIG_SYS_I2C_OFFSET           0x3000
 193#define CONFIG_SYS_FSL_I2C2_SPEED       200000
 194#define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 195#define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 196#define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 197                {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 198                {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 199                {1, {I2C_NULL_HOP} } }
 200
 201#define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 202
 203#if defined(CONFIG_CMD_NAND)
 204#define CONFIG_NAND_KMETER1
 205#define CONFIG_SYS_MAX_NAND_DEVICE      1
 206#define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 207#endif
 208
 209/*
 210 * For booting Linux, the board info and command line data
 211 * have to be in the first 8 MB of memory, since this is
 212 * the maximum mapped by the Linux kernel during initialization.
 213 */
 214#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 215
 216/*
 217 * Core HID Setup
 218 */
 219#define CONFIG_SYS_HID0_INIT            0x000000000
 220#define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 221                                         HID0_ENABLE_INSTRUCTION_CACHE)
 222#define CONFIG_SYS_HID2                 HID2_HBE
 223
 224/*
 225 * MMU Setup
 226 */
 227
 228#define CONFIG_HIGH_BATS        1       /* High BATs supported */
 229
 230/* DDR: cache cacheable */
 231#define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 232                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 233#define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 234                                        BATU_VS | BATU_VP)
 235#define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 236#define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 237
 238/* IMMRBAR & PCI IO: cache-inhibit and guarded */
 239#define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 240                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 241#define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
 242                                        | BATU_VP)
 243#define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 244#define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 245
 246/* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 247#define CONFIG_SYS_IBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 248                                BATL_MEMCOHERENCE)
 249#define CONFIG_SYS_IBAT2U       (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
 250                                BATU_VS | BATU_VP)
 251#define CONFIG_SYS_DBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 252                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 253#define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 254
 255/* FLASH: icache cacheable, but dcache-inhibit and guarded */
 256#define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 257                                        BATL_MEMCOHERENCE)
 258#define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 259                                        BATU_VS | BATU_VP)
 260#define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 261                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 262#define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 263
 264/* Stack in dcache: cacheable, no memory coherence */
 265#define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 266#define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 267                                        BATU_VS | BATU_VP)
 268#define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 269#define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 270
 271/*
 272 * Internal Definitions
 273 */
 274#define BOOTFLASH_START 0xF0000000
 275
 276#define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 277
 278/*
 279 * Environment Configuration
 280 */
 281#define CONFIG_ENV_OVERWRITE
 282#ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 283#define CONFIG_KM_DEF_ENV "km-common=empty\0"
 284#endif
 285
 286#ifndef CONFIG_KM_DEF_ARCH
 287#define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 288#endif
 289
 290#define CONFIG_EXTRA_ENV_SETTINGS \
 291        CONFIG_KM_DEF_ENV                                               \
 292        CONFIG_KM_DEF_ARCH                                              \
 293        "newenv="                                                       \
 294                "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 295                "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 296        "unlock=yes\0"                                                  \
 297        ""
 298
 299#if defined(CONFIG_UEC_ETH)
 300#define CONFIG_HAS_ETH0
 301#endif
 302
 303#endif /* __CONFIG_KM83XX_H */
 304